ADAPTIVE CLOCK SIGNAL MANAGEMENT
    1.
    发明公开

    公开(公告)号:US20240322831A1

    公开(公告)日:2024-09-26

    申请号:US18732693

    申请日:2024-06-04

    CPC classification number: H03L7/24 G06F1/08 G06F1/3296 H03M1/1245

    Abstract: Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. A clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. The controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.

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