Voltage-to-Delay Converter
    1.
    发明申请

    公开(公告)号:US20250141460A1

    公开(公告)日:2025-05-01

    申请号:US18498358

    申请日:2023-10-31

    Abstract: A voltage-to-delay converter includes a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor, and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. First and second input transistors receive first and second input voltages, and are coupled between the top plate of the first and second integrating capacitors, respectively, and a first current source. A discharge current source is coupled to bottom plates of the first and second integrating capacitors. A pulse generator has first and second inputs coupled to the top plate of the first and second integrating capacitors, respectively.

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