公开(公告)号：US20230397413A1

公开(公告)日：2023-12-07

申请号：US17876834

申请日：2022-07-29

Applicant: Texas Instruments Incorporated

Inventor： Krishnanunni B ,  Devraj Rajagopal

IPC: H01L27/112

CPC classification number: H01L27/11286

Abstract: A semiconductor device includes core circuits configured to operate at a core bias potential, input/output (I/O) circuits configured to operate at an I/O bias potential higher than the core bias potential, and a non-volatile memory having a peripheral circuit configured to operate at a memory program bias potential that is higher than the I/O bias potential. The peripheral circuit is also configured to operate at the core bias potential. The peripheral circuit has an input buffer; a threshold potential at an input buffer input node of the input buffer is less than the core bias potential. The peripheral circuit may be manifested as a low voltage supply detection circuit. The peripheral circuit may be manifested as a level shifter circuit. The peripheral circuit may be manifested as a sense circuit. The input buffer may include a drain extended core transistor to provide the desired threshold potential.