公开(公告)号：US20230411262A1

公开(公告)日：2023-12-21

申请号：US18335979

申请日：2023-06-15

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Lopez ,  Jonathan Noquil ,  Jose Carlos Arroyo ,  Makarand R. Kulkarni ,  Guangxu Li

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/565 ,  H01L2021/60022 ,  H01L23/49822 ,  H01L21/563

Abstract: An example microelectronics device package includes: a device mounting layer on an uppermost trace conductor layer on a device side surface of a package substrate, the uppermost trace conductor layer having a first pattern density. The device mounting layer includes a device connection conductor layer; a device mounting land conductor layer on the device connection conductor layer, the device mounting land conductor layer having device mounting land conductors directly contacting the conductors of the device connection conductor layer and having a second pattern density that is less than the first pattern density. A semiconductor die is flip chip mounted to the device mounting layer by solder joints between post connects extending from the semiconductor die and the device mounting land conductors. Mold compound covers the semiconductor die, and the device mounting layer, the mold compound is spaced from the uppermost trace conductor layer by the device mounting layer.