公开(公告)号：US09614506B1

公开(公告)日：2017-04-04

申请号：US14958117

申请日：2015-12-03

Applicant: Texas Instruments Incorporated

Inventor： Michael T. DiRenzo ,  Brian A. Carpenter

IPC: H02M3/157 ,  H03K5/12 ,  G05F1/10

CPC classification number: H03K5/12 ,  G05F1/10

Abstract: Control logic for producing a digital input to a digital-to-analog converter (DAC) in a power converter system. The control logic selects from among a plurality of slew rates during a transition of an output voltage in response to a change in the desired setpoint, so that the output voltage transition follows a desired nominal slew rate. In an initial interval of the transition, a steeper slew rate than the nominal slew rate is selected by the control logic for the digital input to the DAC, until the digital input to the DAC exceeds the nominal slew rate by a first parameter value. At that point, a slew clamp is applied to advance the digital input at the nominal slew rate. Upon the digital input approaching the setpoint value to within a second parameter value, a flatter slew rate than nominal is applied.