公开(公告)号：US12174658B2

公开(公告)日：2024-12-24

申请号：US17892860

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ghotgalkar ,  Rajeev Suvarna ,  Prasanth Viswanathan Pillai ,  Saravanan G

IPC: G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  H03K5/135 ,  H03K5/26

Abstract: An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.

公开(公告)号：US20230213958A1

公开(公告)日：2023-07-06

申请号：US17892860

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ghotgalkar ,  Rajeev Suvarna ,  Prasanth Viswanathan Pillai ,  Saravanan G

IPC: G06F1/08 ,  G06F1/12 ,  H03K5/26 ,  H03K5/135

CPC classification number: G06F1/08 ,  G06F1/12 ,  H03K5/26 ,  H03K5/135

Abstract: An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.

公开(公告)号：US20250117038A1

公开(公告)日：2025-04-10

申请号：US18983491

申请日：2024-12-17

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ghotgalkar ,  Rajeev Suvarna ,  Prasanth Viswanathan Pillai ,  Saravanan G

IPC: G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  H03K5/135 ,  H03K5/26

Abstract: An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.