公开(公告)号：US20150087127A1

公开(公告)日：2015-03-26

申请号：US14559451

申请日：2014-12-03

Applicant: Texas Instruments Incorporated

Inventor： Samuel Zafar Nawaz ,  Shaofeng YU ,  Jeffrey E. BRIGHTON ,  Song ZHAO

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

Abstract translation: 集成电路仅包含源极侧的应力增强区域的晶体管。 在DeMOS晶体管中，仅在源极上形成应力增强区域并且在漏极延伸中不形成应力增强区域增加了漏极延伸区域的电阻，从而能够形成减小面积的DeMOS晶体管。 在MOS晶体管中，通过在源极侧形成应力增强区域，消除来自漏极侧的应力增强区域，降低晶体管泄漏，提高CHC可靠性。

公开(公告)号：US20130292780A1

公开(公告)日：2013-11-07

申请号：US13937398

申请日：2013-07-09

Applicant: Texas Instruments Incorporated

Inventor： Angelo PINTO ,  Frank S. JOHNSON ,  Benjamin P. MCKEE ,  Shaofeng YU

IPC: H01L27/092

CPC classification number: H01L27/0928 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7833

Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.