公开(公告)号：US20180157574A1

公开(公告)日：2018-06-07

申请号：US15577065

申请日：2016-06-06

申请人： The Board of Trustees of the Leland Stanford Junior University ,  New York University

发明人： Subhasish MITRA ,  Clark BARRETT ,  David LIN ,  Eshan SINGH

IPC分类号： G06F11/34 ,  G06F11/22 ,  G06F11/30

CPC分类号： G06F11/3466 ,  G06F11/2236 ,  G06F11/3003 ,  G06F11/3024 ,  G06F11/3079

摘要： Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called “change detectors” which introduce only a small area overhead. Symbolic QED exhibits: 1) A systematic (and automated) approach to inserting “change detectors” during a design phase; 2) Quick Error Detection (QED) tests that detect bugs with short error detection latencies and high coverage; and 3) Formal techniques that enable bug localization and generation of minimal bug traces upon bug detection.

公开(公告)号：US20180165393A1

公开(公告)日：2018-06-14

申请号：US15579577

申请日：2016-06-06

申请人： The Board of Trustees of the Leland Stanford Junior University ,  The Board of Trustees of the University of Illinois

发明人： Subhasish MITRA ,  Keith CAMPBELL ,  David LIN ,  Deming CHEN

IPC分类号： G06F17/50 ,  G06F11/36

摘要： Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. Our methods—which we call Quick Error Detection—Hardware (QED-H)—advantageously quickly detect and fix anomalies (bugs) within SoC hardware components—and in particular customized SoC hardware components that are not necessarily software programmable. Of further advantage, methods according to the present disclosure are compatible with existing Quick Error Detection (QED) techniques while being extensible to target software-programmable components as well. In sharp contrast to prior art methods, method(s) according to the present disclosure represent a new system validation methodology that builds validation checks in both software and hardware components seamlessly and systematically, thus enabling extremely quick error detection and localization for all digital components of the entire SoC advantageously producing productivity and time-to-market gains.