公开(公告)号：US11316656B1

公开(公告)日：2022-04-26

申请号：US17313308

申请日：2021-05-06

申请人： The Johns Hopkins University

发明人： Norman H. Adams ,  Jeffrey A. Boye ,  Adam V. Crifasi ,  Blair C. Fonville ,  Ian M. Hughes ,  Amit Shah ,  Gregory L. Weaver ,  John F. Youssef ,  Darrell A. Zinn

IPC分类号： H04L7/00 ,  H04B1/40 ,  H04B1/69

摘要： A time transfer modem includes a radio frequency integrated circuit (RFIC), a radio frequency (RF) front end, and processing circuitry. The RF front end is configured to receive and up-convert an input for time transfer with a remote station to generate an up-converted timing signal centered at a select frequency that is outside of a frequency range of interest but within an operational frequency range of the RFIC. The RF front end may also be configured to attenuate, via a pre-selection filter, up-converted adjacent signals to generate a filtered timing signal at the select frequency. The RFIC may be configured to down-convert and digitize the filtered timing signal to generate a digitized timing signal for signal processing by the processing circuitry to determine a clock difference between a local clock signal and the digitized timing signal that originated from the remote station.

公开(公告)号：US20220116197A1

公开(公告)日：2022-04-14

申请号：US17313308

申请日：2021-05-06

申请人： The Johns Hopkins University

发明人： Norman H. Adams ,  Jeffrey A. Boye ,  Adam V. Crifasi ,  Blair C. Fonville ,  Ian M. Hughes ,  Amit Shah ,  Gregory L. Weaver ,  John F. Youssef ,  Darrell A. Zinn

IPC分类号： H04L7/00 ,  H04B1/40

摘要： A time transfer modem includes a radio frequency integrated circuit (RFIC), a radio frequency (RF) front end, and processing circuitry. The RF front end is configured to receive and up-convert an input for time transfer with a remote station to generate an up-converted timing signal centered at a select frequency that is outside of a frequency range of interest but within an operational frequency range of the RFIC. The RF front end may also be configured to attenuate, via a pre-selection filter, up-converted adjacent signals to generate a filtered timing signal at the select frequency. The RFIC may be configured to down-convert and digitize the filtered timing signal to generate a digitized timing signal for signal processing by the processing circuitry to determine a clock difference between a local clock signal and the digitized timing signal that originated from the remote station.