公开(公告)号：US20200168659A1

公开(公告)日：2020-05-28

申请号：US16619444

申请日：2018-06-01

申请人： The University Court of the University of Glasgow

发明人： David Robert Sime CUMMING ,  Chengzhi XIE ,  Vincenzo PUSINO

IPC分类号： H01L27/146 ,  H01L31/0304 ,  H01L21/02 ,  H01L31/103

摘要： A method of fabricating a field-effect transistor in which a native oxide layer is removed prior to etching a gate recess. The cleaning step ensures that the etch of the gate recess starts at the same time across an entire sample, such that a uniform gate recess depth and profile can be achieved across an array of field-effect transistors. This results in a highly uniform switch-off voltage for the field-effect transistors in the array.