公开(公告)号：US5257367A

公开(公告)日：1993-10-26

申请号：US554127

申请日：1990-07-17

申请人： Theodore J. Goodlander ,  Raul Kacirek ,  Andras Sarkozy ,  Tamas Hetenyi ,  Janos Selmeczi

发明人： Theodore J. Goodlander ,  Raul Kacirek ,  Andras Sarkozy ,  Tamas Hetenyi ,  Janos Selmeczi

IPC分类号： G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G06F11/22 ,  G06F12/08 ,  G06F13/36 ,  G11B20/18 ,  G06F13/12

CPC分类号： G06F3/0601 ,  G06F11/1008 ,  G06F11/1076 ,  G06F12/0866 ,  G06F13/36 ,  G11B20/1833 ,  G06F11/22 ,  G06F2003/0692 ,  Y10S707/99955

摘要： This invention provides disk drive access control apparatus for connection between a host computer and a plurality of disk drives to provide an asynchronously operating storage system. It also provides increases in performance over earlier versions thereof. There are a plurality of disk drive controller channels connected to respective ones of the disk drives and controlling transfers of data to and from the disk drives, each of the disk drive controller channels includes a cache/buffer memory and a micro-processor unit. An interface and driver unit interfaces with the host computer and there is a central cache memory. Cache memory control logic controls transfers of data from the cache/buffer memory of the plurality of disk drive controller channels to the cache memory and from the cache memory to the cache/buffer memory of the plurality of disk drive controller channels and from the cache memory to the host computer through the interface and driver unit. A central processing unit manages the use of the cache memory by requesting data transfers only of data not presently in the cache memory and by sending high level commands to the disk drive controller channels. A first (data) bus interconnects the plurality of disk drive cache/buffer memories, the interface and driver unit, and the cache memory for the transfer of information therebetween and a second (information and commands) bus interconnects the same elements with the central processing unit for the transfer of control and information therebetween.

摘要翻译： 本发明提供了一种用于在主计算机和多个磁盘驱动器之间连接以提供异步操作的存储系统的磁盘驱动器访问控制装置。 它还提供了比早期版本更高的性能。 存在多个磁盘驱动器控制器通道，其连接到磁盘驱动器的相应磁盘驱动器并且控制向磁盘驱动器传输数据的数据，每个磁盘驱动器控制器通道包括高速缓存/缓冲存储器和微处理器单元。 接口和驱动单元与主机接口，并且有一个中央缓存存储器。 高速缓冲存储器控制逻辑控制数据从多个磁盘驱动器控制器通道的高速缓冲存储器/缓冲存储器到高速缓冲存储器以及从高速缓冲存储器传输到多个磁盘驱动器控制器通道中的高速缓冲存储器/缓冲存储器，并且从缓存存储器 通过接口和驱动单元到主机。 中央处理单元通过仅请求仅当前在高速缓冲存储器中的数据的数据传输并通过向盘驱动器控制器通道发送高电平命令来管理高速缓冲存储器的使用。 第一（数据）总线将多个磁盘驱动器缓存/缓冲存储器，接口和驱动器单元以及高速缓存存储器互连在一起，用于在其间传送信息，而第二（信息和命令）总线将相同的元件与中央处理 其间传送控制单元和信息。

公开(公告)号：US5790774A

公开(公告)日：1998-08-04

申请号：US652637

申请日：1996-05-21

申请人： Andras Sarkozy

发明人： Andras Sarkozy

IPC分类号： G06F11/00

CPC分类号： G06F11/1076 ,  G06F2211/1009

摘要： Table Vectored Parity (TVP) of the present invention is a new method for the allocation of parity check information in multi disk storage systems. This technique permits an optional selection by the end user to store parity check information on a subset of any number of disks ranging from 1 to N, where there are N disks in the system.

摘要翻译： 本发明的表向导奇偶校验（TVP）是在多盘存储系统中分配奇偶校验信息的新方法。 该技术允许最终用户可选地选择将奇偶校验信息存储在从1到N的任何数量的磁盘的子集上，其中系统中存在N个磁盘。

公开(公告)号：US5720027A

公开(公告)日：1998-02-17

申请号：US652636

申请日：1996-05-21

申请人： Andras Sarkozy ,  James Valentino

发明人： Andras Sarkozy ,  James Valentino

IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F11/08 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/22 ,  G06F11/34

CPC分类号： G06F3/0638 ,  G06F11/1076 ,  G06F3/061 ,  G06F3/0689 ,  G06F2211/1054

摘要： A redundant disk computer system providing targeted data broadcast on the data bus to a plurality of devices on the data bus, such as computer central memory and a plurality of storage media disks (parity and data) under control of a real time operating system. Each of the plural disk storage media is each connected to the data bus with a corresponding enhanced disk adapted including a demand page memory of size sufficient to include a selected block of data and arranged to provide access to a selected portion of that data. The redundant array computer operating system provides the control and selected designation of the disk adapters as targeted receivers to read data "broadcast" over the data bus, providing simultaneous transfer of data over the data bus. Each enhanced disk adapter further includes exclusive-OR logic thereon to provide direct calculation of parity from the newly received data and a subsequently received old data on a single subsequent data bus cycle. Thus, according to the present invention, the number of data bus data transfers is reduced and significant improvements in system performance is provided.

摘要翻译： 冗余磁盘计算机系统，其在数据总线上向数据总线上的多个设备提供目标数据广播，诸如在实时操作系统的控制下的计算机中央存储器和多个存储介质盘（奇偶校验和数据）。 多个磁盘存储介质中的每一个各自连接到数据总线，其中相应的增强磁盘适于包括足以包括所选数据块的大小的请求页面存储器，并且被布置成提供对该数据的所选部分的访问。 冗余阵列计算机操作系统将磁盘适配器的控制和选择指定作为目标接收机，通过数据总线读取数据“广播”，从而提供数据总线上的数据的同时传输。 每个增强型磁盘适配器还包括其上的异或逻辑，以在单个后续数据总线周期上提供从新接收到的数据和随后接收的旧数据的直接计算奇偶校验。 因此，根据本发明，减少数据总线数据传送的数量，并提供系统性能的显着改善。

公开(公告)号：US5893919A

公开(公告)日：1999-04-13

申请号：US721090

申请日：1996-09-27

申请人： Andras Sarkozy ,  John O'Brien ,  Gregory Flynn

发明人： Andras Sarkozy ,  John O'Brien ,  Gregory Flynn

IPC分类号： G06F11/10 ,  G06F11/20 ,  G11B17/22

CPC分类号： G06F11/2061 ,  G06F11/1008 ,  G06F11/2087 ,  G06F11/2069 ,  G06F11/2094

摘要： A protection mechanism for use in a mass storage system for providing user selectable levels of protection against data loss wherein storage segments of a plurality of disk drives are organized into at least two functionally separate logical units and a memory management mechanism is responsive to an identification of a logical unit as selected for mirroring by writing a first copy of a data block assigned to a first storage address in a designated logical unit into the assigned storage address in the designated logical unit and writing a second copy of the data block into a second storage address in the disk drives wherein the second storage address is skewed with respect to the first storage address so that the second storage address is located in a disk drive separate from the data disk drive containing the first storage address, and writing at least one parity block containing parity information relating to the data block into a disk drive. The mechanism allows a user to select to write data blocks to the disk drives without corresponding parity information being stored in the disk drives, and to later enter the parity information.

摘要翻译： 一种用于大容量存储系统中的保护机制，用于提供用户可选择的防止数据丢失的级别，其中多个磁盘驱动器的存储段被组织成至少两个功能上分离的逻辑单元，并且存储器管理机制响应于 通过将分配给指定逻辑单元中的第一存储地址的数据块的第一副本写入指定的逻辑单元中的分配的存储地址来选择用于镜像的逻辑单元，并将数据块的第二副本写入第二存储器 磁盘驱动器中的地址，其中第二存储地址相对于第一存储地址偏斜，使得第二存储地址位于与包含第一存储地址的数据盘驱动器分离的磁盘驱动器中，以及写入至少一个奇偶校验块 将与数据块相关的奇偶校验信息包含到磁盘驱动器中。 该机制允许用户选择将数据块写入到磁盘驱动器，而不需要将相应的奇偶校验信息存储在磁盘驱动器中，并且稍后输入奇偶校验信息。

公开(公告)号：US5732238A

公开(公告)日：1998-03-24

申请号：US668622

申请日：1996-06-12

申请人： Andras Sarkozy

发明人： Andras Sarkozy

IPC分类号： G06F12/08

CPC分类号： G06F12/0866 ,  G06F12/0804

摘要： A non-volatile cache mechanism connected to a bus connected for conducting write addresses and data from a host computer to mass storage devices and to a volatile cache wherein each write operation includes a write address and at least one data word. The non-volatile cache mechanism includes a non-volatile memory constructed of a plurality of sub-memories having overlapping read/write cycles for storing the data words, a cache control responsive to the write operations for writing the data words into the nonvolatile memory in parallel with receipt of the data words into the volatile cache, and a cache index for storing index entries relating write addresses of write operations on the bus with corresponding storage addresses of the data words in the non-volatile memory. The cache control is responsive to a write operation for reading the index entries to identify and select at least one available storage address in the non-volatile memory, generating at least one index entry relating the write address of the current write operation and the selected storage addresses in the non-volatile memory, and writing the data words into the non-volatile memory. The cache control is responsive to flush addresses to the volatile cache for indexing the cache index to identify cache entries corresponding to the flush addresses and invalidating the corresponding cache entries.

摘要翻译： 连接到总线的非易失性高速缓存机构，用于从主计算机向大容量存储设备和易失性高速缓冲存储器执行写地址和数据，其中每个写操作包括写地址和至少一个数据字。 非易失性缓存机构包括由具有用于存储数据字的重叠读/写周期的多个子存储器构成的非易失性存储器，响应用于将数据字写入非易失性存储器的写入操作的高速缓存控制 与将数据字接收到易失性高速缓存中并且与缓存索引相关联，缓存索引用于存储与总线上的写入操作的写入地址相关联的非易失性存储器中的数据字的相应存储地址的索引条目。 高速缓存控制响应于用于读取索引条目的写入操作以识别和选择非易失性存储器中的至少一个可用存储地址，生成与当前写入操作的写入地址相关联的至少一个索引条目和所选择的存储 非易失性存储器中的地址，以及将数据字写入非易失性存储器。 高速缓存控制响应于易失性高速缓存的刷新地址，用于索引高速缓存索引以识别与刷新地址对应的高速缓存条目并使相应的高速缓存条目无效。