公开(公告)号：US5416897A

公开(公告)日：1995-05-16

申请号：US117485

申请日：1993-09-07

申请人： Thomas M. Albers ,  John V. Eberst ,  Darwin Fontenot ,  Richard L. Pyra ,  Mark W. Welker ,  Wood, Paul B. ,  Jack E. Bresenham

发明人： Thomas M. Albers ,  John V. Eberst ,  Darwin Fontenot ,  Richard L. Pyra ,  Mark W. Welker ,  Wood, Paul B. ,  Jack E. Bresenham

IPC分类号： G09G5/20 ,  G06T11/20

CPC分类号： G06T11/203

摘要： Circuitry for drawing lines includes a video memory for storing pixel data and circuitry for generating a sequence of addresses defining a line of pixels in the video memory. A first memory stores a sequence of pattern units corresponding to the generated sequence of addresses. A second memory stores a value indicating a current pattern unit. Writing circuitry writes to the video memory at a generated address responsive to a current pattern unit. A third memory stores a control value which is accessed by update circuitry for updating the second memory to indicate the next pattern unit. The update circuitry may selectively update the second memory to the sequential pattern unit or reset the second memory to a predetermined pattern unit.

摘要翻译： 用于绘制线的电路包括用于存储像素数据的视频存储器和用于产生定义视频存储器中的像素线的地址序列的电路。 第一存储器存储对应于所生成的地址序列的模式单元序列。 第二存储器存储指示当前图案单元的值。 写入电路响应于当前模式单元以产生的地址写入视频存储器。 第三存储器存储由更新电路访问的控制值，用于更新第二存储器以指示下一个模式单元。 更新电路可以选择性地将第二存储器更新为顺序模式单元或将第二存储器复位到预定模式单元。

公开(公告)号：US5613054A

公开(公告)日：1997-03-18

申请号：US520040

申请日：1995-08-28

申请人： Thomas M. Albers ,  John V. Eberst ,  Darwin Fontenot ,  Richard L. Pyra ,  Mark W. Welker ,  Paul B. Wood ,  Jack E. Bresenham

发明人： Thomas M. Albers ,  John V. Eberst ,  Darwin Fontenot ,  Richard L. Pyra ,  Mark W. Welker ,  Paul B. Wood ,  Jack E. Bresenham

IPC分类号： G09G5/20 ,  G06T11/20 ,  G06F15/00

CPC分类号： G06T11/203

摘要： Line draw circuitry receives parameters defining first and second endpoints of a line and calculates line parameters based on the first and second endpoints. The line parameters are then stored in a memory. A "calculate-only" control signals determines whether a line is drawn immediately after calculation (and storing) of the end parameters or whether the line is drawn responsive to a subsequent "start" signal. If the line is to be drawn responsive to the start signal, the line parameters may be modified prior to drawing the line.

摘要翻译： 线绘制电路接收定义线的第一和第二端点的参数，并基于第一和第二端点计算线路参数。 然后将线路参数存储在存储器中。 “仅计算”控制信号确定在计算（并存储）结束参数之后立即绘制线，还是响应于随后的“开始”信号绘制线。 如果要响应于起始信号来绘制线，则可以在绘制线之前修改线参数。

公开(公告)号：US5613053A

公开(公告)日：1997-03-18

申请号：US823529

申请日：1992-01-21

申请人： Thomas M. Albers ,  John V. Eberst ,  Darwin Fontenot ,  Richard L. Pyra ,  Mark W. Welker ,  Paul B. Wood ,  Jack E. Bresenham

发明人： Thomas M. Albers ,  John V. Eberst ,  Darwin Fontenot ,  Richard L. Pyra ,  Mark W. Welker ,  Paul B. Wood ,  Jack E. Bresenham

IPC分类号： G06T11/20 ,  G06T11/00

CPC分类号： G06T11/203

摘要： A graphics processor uses a line draw facility to receive first and second values indicative of the coordinates of respective first and second end points of a line. The reception of the second value is sensed by the line draw facility and line data is generated responsive to the sensing of the second value.

摘要翻译： 图形处理器使用线绘制工具来接收指示线的相应第一和第二端点的坐标的第一和第二值。 第二值的接收由线条绘制设备感测，并且响应于对第二值的感测产生线数据。

公开(公告)号：US5570107A

公开(公告)日：1996-10-29

申请号：US388331

申请日：1995-02-14

申请人： Paul B. Wood ,  Thomas M. Albers ,  Stephen B. Preston

发明人： Paul B. Wood ,  Thomas M. Albers ,  Stephen B. Preston

IPC分类号： G09G5/06 ,  G09G5/08 ,  G09G1/28

CPC分类号： G09G5/08 ,  G09G5/06

摘要： A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. Highlighted pixels in a cursor are displayed by inverting the output of the color palette RAM at cursor locations, for example by way of an exclusive-OR function of the color palette RAM output and a bit corresponding to the comparison of the display location and the desired cursor location. Inversion of the output of the color palette RAM results in higher contrast pixels within the cursor.

公开(公告)号：US5389947A

公开(公告)日：1995-02-14

申请号：US26207

申请日：1993-03-02

申请人： Paul B. Wood ,  Thomas M. Albers ,  Stephen B. Preston

发明人： Paul B. Wood ,  Thomas M. Albers ,  Stephen B. Preston

IPC分类号： G09G5/06 ,  G09G5/08 ,  G09G1/28

CPC分类号： G09G5/08 ,  G09G5/06

摘要： A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. Highlighted pixels in a cursor are displayed by inverting the output of the color palette RAM at cursor locations, for example by way of an exclusive-OR function of the color palette RAM output and a bit corresponding to the comparison of the display location and the desired cursor location. Inversion of the output of the color palette RAM results in higher contrast pixels within the cursor.

摘要翻译： 公开了包括视频数模转换器的图形子系统。 高速振荡器以要显示像素的频率产生像素时钟信号。 包括在视频DAC中的分频器是一个分频器，它提供一个输出时钟信号，该输出时钟信号的周期是像素时钟信号的倍数，该倍数对应于由视频DAC提供的像素数据的复用电平; 这个多重可以相等的统一。 系统中的视频控制器接收输出时钟信号，并产生时钟信号以控制帧存储器的串行端口，并且还控制视频DAC中第一级的锁存。 视频DAC中的第一级锁存器锁存来自帧存储器的多个像素数据，并且视频DAC中的多路复用器将数据呈现为彩色调色板RAM或彩色非多路复用模式下的调色板RAM周围， 根据像素时钟信号。 光标中的突出显示的像素通过将调色板RAM的输出在光标位置反转来显示，例如通过调色板RAM输出的异或功能和对应于显示位置与期望的比较的位 光标位置。 调色板RAM的输出反转导致光标内的较高对比度像素。

公开(公告)号：US5261095A

公开(公告)日：1993-11-09

申请号：US420085

申请日：1989-10-11

申请人： Douglas C. Crawford ,  Michael A. Denio ,  Thomas M. Albers

发明人： Douglas C. Crawford ,  Michael A. Denio ,  Thomas M. Albers

IPC分类号： G06F9/40 ,  G06F9/44 ,  G06F9/00

CPC分类号： G06F9/4425 ,  G06F8/45

摘要： A method of partitioning a software program, so that a main program may be executed on a first processor, and at least one designated function may be executed on a second processor. The subprogram to be executed by the second processor is selected from a main program associated with a first processor and identified globally to both processors. The subprogram is given a call from the main program that creates a software environment that is compatible to both processors. More specifically, the method entails creating an argument passing means, via the function call, so that relevant information about the subprogram parameters may be communicated to the second processor.

摘要翻译： 一种分割软件程序的方法，使得可以在第一处理器上执行主程序，并且可以在第二处理器上执行至少一个指定的功能。 要从第二处理器执行的子程序从与第一处理器相关联的主程序中选择并且全局地标识给两个处理器。 该子程序被授予来自主程序的调用，该程序创建与两个处理器兼容的软件环境。 更具体地，该方法需要通过函数调用创建参数传递装置，使得关于子程序参数的相关信息可以被传送到第二处理器。