Method and apparatus for microprocessor debugging
    3.
    发明授权
    Method and apparatus for microprocessor debugging 失效
    微处理器调试方法和装置

    公开(公告)号:US5892897A

    公开(公告)日:1999-04-06

    申请号:US795581

    申请日:1997-02-05

    IPC分类号: G06F11/16 G06F11/18 G06F11/00

    摘要: A trailer microprocessor in a debugging tool runs code a known number of cycles behind a master and shadow pair of processors. A pipeline queues up bus activity from the shadow processor a number of cycles, and then outputs those signals to the trailer microprocessor to execute the same code and signals as the master and shadow microprocessors a known number of cycles behind. The outputs of the master and shadow microprocessors are compared and the trailer microprocessor is halted, along with the master and shadow, when a "mismatch" occurs between the outputs of the master and shadow processors. When the internal states of all three processors are scanned, the differences in the internal state of the shadow processor before and at a failure can be theoretically compared. The trailer microprocessor may be stepped cycle-by-cycle up to and past the point of failure of the shadow processor for further analysis.

    摘要翻译: 调试工具中的拖车微处理器在主控和阴影对处理器之后运行已知数量的循环代码。 流水线将影子处理器的总线活动排队多个周期,然后将这些信号输出到尾部微处理器,以执行与主影子和阴影微处理器相同的代码和信号,已知数量的周期。 当主控和阴影处理器的输出之间发生“不匹配”时,比较主影和微处理器的输出以及拖尾微处理器以及主机和阴影。 当扫描所有三个处理器的内部状态时,理论上可以比较影子处理器在故障之前和失败时内部状态的差异。 拖车微处理器可以逐渐地逐步循环,直到影子处理器的故障点进行进一步的分析。