公开(公告)号：US07876141B2

公开(公告)日：2011-01-25

申请号：US12251376

申请日：2008-10-14

Applicant: Benoît Lasbouygues ,  Sylvain Clerc ,  Alain Artieri ,  Thomas Zounes ,  Françoise Jacquet

Inventor： Benoît Lasbouygues ,  Sylvain Clerc ,  Alain Artieri ,  Thomas Zounes ,  Françoise Jacquet

IPC: H03K5/01

CPC classification number: H03K5/135

Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.

Abstract translation: 用于至少两个寄存器的同步脉冲发生器，包括用于接收时钟信号的第一输入和用于在所述寄存器的时钟输入端递送脉冲的至少一个输出，以及用于接收所述时钟信号的至少一个第二输入 独立于时钟信号强制输出的信号使所述寄存器透明。

公开(公告)号：US20060114029A1

公开(公告)日：2006-06-01

申请号：US11333429

申请日：2006-01-17

Applicant: Scott Anderson ,  Razak Hossain ,  Thomas Zounes

Inventor： Scott Anderson ,  Razak Hossain ,  Thomas Zounes

IPC: H03K19/096

CPC classification number: G01R31/318541

Abstract: A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The timing circuit also causes the output of the circuit to be timed with a state change in the clock signal to provide a domino logic output signal. Either a data signal or a test signal are multiplexed to the input of the driving circuit to produce respectively the domino logic output signal or a test output signal. A static logic circuit receives the test output signal to produce a test signal output.

公开(公告)号：US20050006670A1

公开(公告)日：2005-01-13

申请号：US10604318

申请日：2003-07-10

Applicant: Thomas Zounes

Inventor： Thomas Zounes

IPC: H01L27/02 ,  H01L27/10 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: A cell library for designing integrated domino circuits has a first library portion with a plurality of selectable logic circuits having different transistor sizes and/or logic functions for selection according to desired logic function and parametric characteristics. A second library portion includes a plurality of selectable prechargeable driver circuits. Each of the driver circuits is configured to be connectable to an output of a selected one of the logic circuits. The driver circuits also have at least different transistor sizes. Standard FET devices may be constructed to precharge the output node of the selected logic circuit in the design of a domino logic circuit.

Abstract translation: 用于设计集成多米诺骨牌电路的单元库具有第一库部分，具有多个具有不同晶体管尺寸和/或逻辑功能的可选逻辑电路，用于根据期望的逻辑功能和参数特性进行选择。 第二库部分包括多个可选择的可预充电驱动器电路。 每个驱动器电路被配置为可连接到所选逻辑电路的输出端。 驱动器电路还具有至少不同的晶体管尺寸。 可以构造标准FET器件，以在多米诺逻辑电路的设计中对所选择的逻辑电路的输出节点进行预充电。

公开(公告)号：US20090146720A1

公开(公告)日：2009-06-11

申请号：US12251376

申请日：2008-10-14

Applicant: Benoit Lasbouygues ,  Sylvain Clerc ,  Alain Artieri ,  Thomas Zounes ,  Francoise Jacquet

Inventor： Benoit Lasbouygues ,  Sylvain Clerc ,  Alain Artieri ,  Thomas Zounes ,  Francoise Jacquet

IPC: H03K3/00

CPC classification number: H03K5/135

Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.

Abstract translation: 用于至少两个寄存器的同步脉冲发生器，包括用于接收时钟信号的第一输入和用于在所述寄存器的时钟输入端递送脉冲的至少一个输出，以及用于接收所述时钟信号的至少一个第二输入 独立于时钟信号强制输出的信号使所述寄存器透明。

公开(公告)号：US20080238473A1

公开(公告)日：2008-10-02

申请号：US11691880

申请日：2007-03-27

Applicant: Thomas Zounes

Inventor： Thomas Zounes

IPC: H03K19/01

CPC classification number: H03K19/01742 ,  G01R31/31713 ,  H03K3/356121 ,  H03K3/35625

Abstract: A push-pull pulse register circuit. The push-pull pulse register circuit includes a first logic inverter having first-inverter input and first-inverter output, a second logic inverter having second-inverter input and second-inverter output, a third logic inverter having third-inverter input and third-inverter output and configured to receive logic input data at the third-inverter input, a first logic gate having first-gate input, first-gate output, and first-gate control input, and a second logic gate having second-gate input, second-gate output, and second-gate control input. The third-inverter input is coupled to the first-gate input; the third-inverter output is coupled to the second-gate input; the second-inverter input is coupled to the second-gate output and the first-inverter output; the second-inverter output is coupled to the first-gate output and the first-inverter input; the first-gate control input is coupled to the second-gate control input; and the first-gate and the second-gate control inputs are configured to receive a clock pulse.

Abstract translation: 推挽脉冲寄存器电路。 推挽脉冲寄存器电路包括具有第一反相器输入和第一反相器输出的第一逻辑反相器，具有第二反相器输入和第二反相器输出的第二逻辑反相器，具有第三反相器输入和第三反相器输入的第三逻辑反相器， 逆变器输出并且被配置为在第三反相器输入处接收逻辑输入数据，具有第一栅极输入，第一栅极输出和第一栅极控制输入的第一逻辑门，以及具有第二栅极输入的第二逻辑门，第二栅极输入 门输出和二门控制输入。 第三反相器输入耦合到第一栅极输入; 第三反相器输出耦合到第二栅极输入; 第二逆变器输入耦合到第二栅极输出和第一反相器输出; 第二逆变器输出耦合到第一栅极输出和第一反相器输入; 第一栅极控制输入耦合到第二栅极控制输入; 并且第一栅极和第二栅极控制输入被配置为接收时钟脉冲。

公开(公告)号：US20060253808A1

公开(公告)日：2006-11-09

申请号：US11421035

申请日：2006-05-30

Applicant: Thomas Zounes

Inventor： Thomas Zounes

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: A cell library for designing integrated domino circuits has a first library portion with a plurality of selectable logic circuits having different transistor sizes and/or logic functions for selection according to desired logic function and parametric characteristics. A second library portion includes a plurality of selectable prechargeable driver circuits. Each of the driver circuits is configured to be connectable to an output of a selected one of the logic circuits. The driver circuits also have at least different transistor sizes. Standard FET devices may be constructed to precharge the output node of the selected logic circuit in the design of a domino logic circuit.

Abstract translation: 用于设计集成多米诺骨牌电路的单元库具有第一库部分，具有多个具有不同晶体管尺寸和/或逻辑功能的可选逻辑电路，用于根据期望的逻辑功能和参数特性进行选择。 第二库部分包括多个可选择的可预充电驱动器电路。 每个驱动器电路被配置为可连接到所选逻辑电路的输出端。 驱动器电路还具有至少不同的晶体管尺寸。 可以构造标准FET器件，以在多米诺逻辑电路的设计中对所选择的逻辑电路的输出节点进行预充电。