公开(公告)号：US20120227016A1

公开(公告)日：2012-09-06

申请号：US13471061

申请日：2012-05-14

申请人： Tomoyuki ISHIZU ,  Kyouji YAMASHITA ,  Gaku SUZUKI

发明人： Tomoyuki ISHIZU ,  Kyouji YAMASHITA ,  Gaku SUZUKI

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5036

摘要： The present disclosure provides a method of performing circuit simulation of electrical characteristics of a transistor formed on a semiconductor substrate using calculators, each of which includes a memory. A first calculator receives mask layout data and distance-dependent data indicating a distance from the target transistor. Then, a second calculator calculates an area ratio of a layout pattern of a predetermined mask from the received mask layout data, and calculates a parameter α based on the area ratio and the distance-dependent data. Then, the second calculator B calculates a change ΔP in the electrical characteristics of the transistor based on the parameter α. This configuration provides highly accurate circuit simulation of the electrical characteristics of the transistor, which depend on variations in temperature distribution of the semiconductor substrate during heat treatment due to the mask layout pattern around the transistor.

摘要翻译： 本公开提供了一种使用计算器来执行形成在半导体衬底上的晶体管的电特性的电路仿真的方法，每个都包括存储器。 第一计算器接收掩模布局数据和指示距离目标晶体管的距离的距离相关数据。 然后，第二计算器从接收到的掩模布局数据计算预定掩模的布局图案的面积比，并且基于面积比和距离相关数据来计算参数α。 然后，第二计算器B基于参数α计算晶体管的电特性中的变化＆Dgr; P。 该配置提供了晶体管的电特性的高度精确的电路仿真，其取决于由于晶体管周围的掩模布局图案而在热处理期间半导体衬底的温度分布的变化。

公开(公告)号：US20110204448A1

公开(公告)日：2011-08-25

申请号：US13034160

申请日：2011-02-24

申请人： Tomoyuki ISHIZU

发明人： Tomoyuki ISHIZU

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/823807 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/6659

摘要： In a semiconductor device having paired transistors, an imbalance in characteristics of the paired transistors is reduced or prevented while an increase in circuit area is reduced or prevented. First and second transistors have first and second regions having the same active region pattern, and third and fourth transistors have third and fourth regions having the same active region pattern. The active regions of the third and fourth transistors have a longer length in the channel length direction than that of the active regions of the first and second transistors. The third and fourth regions have a narrower width in the channel length direction than that of the first and second regions.

摘要翻译： 在具有成对晶体管的半导体器件中，减少或防止成对晶体管的特性不平衡，同时降低或防止电路面积的增加。 第一和第二晶体管具有第一和第二区域具有相同的有源区域图案，并且第三和第四晶体管具有相同的有源区域图案的第三和第四区域。 第三和第四晶体管的有源区在沟道长度方向的长度比第一和第二晶体管的有源区的长度长。 第三区域和第四区域的沟道长度方向上的宽度比第一区域和第二区域宽。