公开(公告)号：US20200350291A1

公开(公告)日：2020-11-05

申请号：US16916979

申请日：2020-06-30

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Ryota KATSUMATA ,  Jun IIJIMA ,  Tetsuya SHIMIZU ,  Takamasa USUI ,  Genki FUJITA

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20190312012A1

公开(公告)日：2019-10-10

申请号：US16390639

申请日：2019-04-22

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Ryota KATSUMATA ,  Jun IIJIMA ,  Tetsuya SHIMIZU ,  Takamasa USUI ,  Genki FUJITA

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/00

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20190074230A1

公开(公告)日：2019-03-07

申请号：US15901115

申请日：2018-02-21

Applicant: Toshiba Memory Corporation

Inventor： Takahito NISHIMURA ,  Suigen KANDA ,  Takamasa USUI ,  Masayoshi TAGAMI ,  Jun llJIMA

IPC: H01L21/66 ,  H01L21/027 ,  B29C59/02 ,  G03F7/00 ,  G03F7/16

Abstract: According to an embodiment, a template includes a flat plate-shaped first member, a flat plate-shaped second member including a pattern arrangement face, and a flat plate-shaped third member provided with an opening at a position corresponding to an arrangement position of the second member. The template is dividable at a position of at least one of a first boundary between the first member and the second member and a second boundary between the first member and the third member.