公开(公告)号：US20090304138A1

公开(公告)日：2009-12-10

申请号：US12409280

申请日：2009-03-23

申请人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Yung-chih Chen ,  Po-yuan Liu

发明人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Yung-chih Chen ,  Po-yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A shift register and a shift register unit for diminishing clock coupling effect are introduced herein. Each stage shift register unit includes at least one pull-up driving module, a pull-up module, at least one pull-down module and a pull-down driving module. Before a waveform of either a first clock signal or a second clock signal employed by the pull-up module transits into a rising edge, the pull-down driving module employs a first periodic signal to turn on the pull-down module in advance for a specific period, and/or before the waveform of the first or second clock signal employed by the pull-up module transits into a falling edge, the pull-down driving module employs a second periodic signal to turn off the pull-down module in advance for a specific period. Accordingly, the pull-down module can gain a sufficient capability against the clock coupling effect so as to optimize the waveform outputted from the shift register unit.

摘要翻译： 本文介绍了一种用于减小时钟耦合效应的移位寄存器和移位寄存器单元。 每级移位寄存器单元包括至少一个上拉驱动模块，上拉模块，至少一个下拉模块和下拉驱动模块。 在由上拉模块采用的第一时钟信号或第二时钟信号的波形进入上升沿之前，下拉驱动模块采用第一周期信号来预先为下拉模块接通 在上拉模块采用的第一或第二时钟信号的波形转入下降沿之前和/或之前，下拉驱动模块采用第二周期信号预先关闭下拉模块 在一段特定的时期。 因此，下拉模块可以针对时钟耦合效应获得足够的能力，以优化从移位寄存器单元输出的波形。

公开(公告)号：US07949086B2

公开(公告)日：2011-05-24

申请号：US12480020

申请日：2009-06-08

申请人： Tsung-ting Tsai ,  Yung-chih Chen

发明人： Tsung-ting Tsai ,  Yung-chih Chen

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A shift register includes a plurality of register units cascade-connected with each other. Each register unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit turns on in response to a driving pulse from a previous register unit and a second clock signal, and turns off in response to a third clock signal. The pull-down driving circuit which is coupled to an input node of the pull-down circuit, turns on in response to a first clock signal, and turns off in response to a the first clock signal or output of the pull-up driving circuit.

摘要翻译： 移位寄存器包括彼此级联的多个寄存器单元。 每个寄存器单元包括上拉电路，上拉驱动电路，下拉电路和下拉驱动电路。 耦合到第一时钟信号的上拉电路用于提供输出信号。 上拉驱动电路响应于来自先前寄存器单元和第二时钟信号的驱动脉冲而导通，并响应于第三时钟信号而截止。 耦合到下拉电路的输入节点的下拉驱动电路响应于第一时钟信号而导通，并响应于第一时钟信号或上拉驱动电路的输出而断开 。

公开(公告)号：US07688934B2

公开(公告)日：2010-03-30

申请号：US12409280

申请日：2009-03-23

申请人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Yung-chih Chen ,  Po-yuan Liu

发明人： Tsung-ting Tsai ,  Ming-sheng Lai ,  Yung-chih Chen ,  Po-yuan Liu

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A shift register and a shift register unit for diminishing clock coupling effect are introduced herein. Each stage shift register unit includes at least one pull-up driving module, a pull-up module, at least one pull-down module and a pull-down driving module. Before a waveform of either a first clock signal or a second clock signal employed by the pull-up module transits into a rising edge, the pull-down driving module employs a first periodic signal to turn on the pull-down module in advance for a specific period, and/or before the waveform of the first or second clock signal employed by the pull-up module transits into a falling edge, the pull-down driving module employs a second periodic signal to turn off the pull-down module in advance for a specific period. Accordingly, the pull-down module can gain a sufficient capability against the clock coupling effect so as to optimize the waveform outputted from the shift register unit.

摘要翻译： 本文介绍了一种用于减小时钟耦合效应的移位寄存器和移位寄存器单元。 每级移位寄存器单元包括至少一个上拉驱动模块，上拉模块，至少一个下拉模块和下拉驱动模块。 在由上拉模块采用的第一时钟信号或第二时钟信号的波形进入上升沿之前，下拉驱动模块采用第一周期信号来预先为下拉模块接通 在上拉模块采用的第一或第二时钟信号的波形转入下降沿之前和/或之前，下拉驱动模块采用第二周期信号预先关闭下拉模块 在一段特定的时期。 因此，下拉模块可以针对时钟耦合效应获得足够的能力，以优化从移位寄存器单元输出的波形。

公开(公告)号：US20090304139A1

公开(公告)日：2009-12-10

申请号：US12480020

申请日：2009-06-08

申请人： Tsung-ting Tsai ,  Yung-chih Chen

发明人： Tsung-ting Tsai ,  Yung-chih Chen

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A shift register includes a plurality of register units cascade-connected with each other. Each register unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit turns on in response to a driving pulse from a previous register unit and a second clock signal, and turns off in response to a third clock signal. The pull-down driving circuit which is coupled to an input node of the pull-down circuit, turns on in response to a first clock signal, and turns off in response to a the first clock signal or output of the pull-up driving circuit.

摘要翻译： 移位寄存器包括彼此级联的多个寄存器单元。 每个寄存器单元包括一个上拉电路，一个上拉驱动电路，一个下拉电路和一个下拉驱动电路。 耦合到第一时钟信号的上拉电路用于提供输出信号。 上拉驱动电路响应于来自先前寄存器单元和第二时钟信号的驱动脉冲而导通，并响应于第三时钟信号而截止。 耦合到下拉电路的输入节点的下拉驱动电路响应于第一时钟信号而导通，并且响应于第一时钟信号或上拉驱动电路的输出而断开 。