公开(公告)号：US06261904B1

公开(公告)日：2001-07-17

申请号：US09596449

申请日：2000-06-19

申请人： Tuan Pham ,  Bharath Rangarajan ,  Mike Templeton

发明人： Tuan Pham ,  Bharath Rangarajan ,  Mike Templeton

IPC分类号： H01L21336

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual ONO floating gates with an isolation spacer between floating gates. Processes for making the memory device according to the invention are also provided.

摘要翻译： 本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。 根据本发明的一个方面，提供了一种存储器件，其包括具有在浮置栅极之间具有隔离间隔物的双ONO浮置栅极的浮栅晶体管。 还提供了用于制造根据本发明的存储器件的工艺。

公开(公告)号：US06610580B1

公开(公告)日：2003-08-26

申请号：US09563179

申请日：2000-05-02

申请人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

发明人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

IPC分类号： H01L2176

CPC分类号： H01L27/11521 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/11517

摘要： In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back. Through the use of the preferred embodiment of the present invention, a shallow trench isolation process is implemented as opposed to LOCOS process, thereby reducing the occurrence of polyl stringers in the channel area. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent regions is substantially reduced.

摘要翻译： 在本发明的第一方面，公开了一种闪存阵列。 闪存阵列包括包含有源区的衬底，其中有源区由氮化物层限定，氮化物层包括顶表面。 闪存阵列还包括衬底中的浅沟槽，每个浅沟槽包括一层氧化物，氧化层具有顶表面，其中氧化层的顶表面和氮化层的顶表面 在基本相同的平面和通道区域上，其中通道区域中多边形桁条的出现被大大减少。 在本发明的第二方面中，公开了一种用于制造闪存阵列的方法和系统。 该方法包括以下步骤：在衬底上提供氮化物层，在衬底中形成沟槽，然后在沟槽中生长一层氧化物。 最后，氧化层被抛光。 通过使用本发明的优选实施例，与LOCOS工艺相反，实现了浅沟槽隔离工艺，从而减少了通道区域中多边形的发生。 因此，相邻区域之间不需要的电短路径的发生显着减少。