Low voltage programmable and erasable flash EEPROM
    1.
    发明授权
    Low voltage programmable and erasable flash EEPROM 有权
    低电压可编程和可擦除闪存EEPROM

    公开(公告)号:US06703659B2

    公开(公告)日:2004-03-09

    申请号:US10338221

    申请日:2003-01-08

    IPC分类号: H01L2976

    摘要: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions where the junctions are deeper and less abrupt than the drain junctions to complete the Flash EEPROM memory cells in the integrated circuit device.

    摘要翻译: 实现了一种制造和编程和擦除闪存EEPROM存储单元的新方法。 提供半导体衬底。 形成覆盖所述半导体衬底的隧道氧化物层。 沉积在隧道氧化物层上的第一多晶硅层。 沉积在第一多晶硅层上的多晶硅层。 第二多晶硅层沉积在层间氧化物层的上方。 对第二多晶硅层,多晶硅氧化物层,第一多晶硅层和隧道氧化物层进行图案化以形成用于计划的闪存EEPROM存储单元的控制栅极和浮置栅极。 离子被植入以形成半导体衬底中计划的闪存EEPROM存储单元的漏极结,其中漏极接点较浅而突然。 植入离子以形成与排水结相邻的倾斜的袋结。 成角度的凹穴接合部以相对于半导体衬底的非垂直角注入,并且与掺杂的漏极结相反。 离子被植入以形成其中结点比漏极结更深并且不太突然的源结,以完成集成电路器件中的闪存EEPROM存储单元。