公开(公告)号：US20230386893A1

公开(公告)日：2023-11-30

申请号：US17843089

申请日：2022-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Tsai HUNG ,  Yi LIU ,  Guo-Hai ZHANG ,  Ching-Hwa TEY

IPC: H01L21/762 ,  H01L27/12 ,  H01L23/00

CPC classification number: H01L21/76251 ,  H01L27/1203 ,  H01L23/562 ,  H01L23/564

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

公开(公告)号：US20240105502A1

公开(公告)日：2024-03-28

申请号：US18537861

申请日：2023-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Tsai HUNG ,  Yi LIU ,  Guo-Hai ZHANG ,  Ching-Hwa TEY

IPC: H01L21/762 ,  H01L23/00 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L23/562 ,  H01L23/564 ,  H01L27/1203

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

公开(公告)号：US20220367609A1

公开(公告)日：2022-11-17

申请号：US17364935

申请日：2021-07-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Ji CHEN ,  Jing FENG ,  Xiao-Hong JIANG ,  Ching-Hwa TEY

IPC: H01L49/02

Abstract: A method for fabricating a MOMCAP includes steps as follows: An Nth metal layer is formed on a substrate according to an Nth expected capacitance value of the Nth metal layer. An Nth capacitance error value between an Nth actual capacitance value of the Nth metal layer and the Nth expected capacitance value is calculated. An N+1th expected capacitance value of an N+1th metal layer is adjusted to form an N+1th actual capacitance value according to the Nth capacitance error value, and the N+1th metal layer with an N+1th actual capacitance value is formed on the Nth metal layer according to the adjusted N+1th expected capacitance value, to make the sum of the Nth actual capacitance value and the N+1th actual capacitance value equal to the sum of the Nth expected capacitance value and the N+1th expected capacitance value. N is an integer greater than 1.