公开(公告)号：US20240162291A1

公开(公告)日：2024-05-16

申请号：US18077203

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-In Wu ,  Yu-Ming Lin ,  Cheng-Tung Huang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7855 ,  H01L29/78696

Abstract: A transistor with a fin structure and a nanosheet includes a fin structure. A first gate device is disposed on the fin structure. A first source/drain layer is disposed at one side of the first gate device. A first source/drain layer is on the fin structure and extends into the fin structure. A second source/drain layer is disposed at another side of the first gate device. The second source/drain layer is on the fin structure and extends into the fin structure. A nanosheet is disposed above the first gate device, between the first source/drain layer and the second source/drain layer, and contacts the first source/drain layer and the second source/drain layer. A second gate device surrounds the nanosheet.

公开(公告)号：US20250126807A1

公开(公告)日：2025-04-17

申请号：US18499223

申请日：2023-11-01

Applicant: United Microelectronics Corp.

Inventor： Ching-In Wu

IPC: H10B63/00 ,  H10N70/00

Abstract: A resistive memory structure including a transistor device and a resistive memory device is provided. The transistor device includes a gate. The resistive memory device is electrically connected to the gate of the transistor device.