公开(公告)号：US20210320109A1

公开(公告)日：2021-10-14

申请号：US16843864

申请日：2020-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fang-Sheng Chou ,  Ching Chang

IPC: H01L27/11 ,  G11C29/12

Abstract: The present invention provides a test key structure, the test key structure a substrate, a plurality of test key cells disposed on the substrate, wherein each test key cell includes a first gate structure arranged along a first direction (X-axis), a first diffusion region, a second diffusion region, a connection diffusion region and a share contact arranged along a second direction (Y-axis), wherein the first gate structure crosses over the first diffusion region to form a pull-up transistor (PU), the second gate structure crosses over the second diffusion region to form a pull-down transistor (PD), and wherein the plurality of share contacts and the plurality of connection diffusion regions of the plurality of test key cells are electrically connected to each other.