公开(公告)号：US09245972B2

公开(公告)日：2016-01-26

申请号：US14016393

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Yuan-Chi Pai ,  Fong-Lung Chuang

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66484 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

Abstract translation: 提供一种制造半导体器件的方法。 提供分别形成在第一区域和第二区域中的具有第一栅极和第二栅极的衬底。 在衬底上形成底层以覆盖第一区域中的第一栅极和第二区域中的第二栅极。 在第一区域中的底层上形成具有预定厚度的图案化掩模。 通过图案化掩模去除对应于第二区域中的第二栅极的底层以暴露第二栅极，其中对应于第一区域中的第一栅极的底层被部分消耗以暴露第一栅极的部分。

公开(公告)号：US20150064861A1

公开(公告)日：2015-03-05

申请号：US14016393

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Yuan-Chi Pai ,  Fong-Lung Chuang

IPC: H01L29/66

CPC classification number: H01L29/66484 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

Abstract translation: 提供一种制造半导体器件的方法。 提供了分别形成在第一区域和第二区域中的具有第一栅极和第二栅极的衬底。 在衬底上形成底层以覆盖第一区域中的第一栅极和第二区域中的第二栅极。 在第一区域中的底层上形成具有预定厚度的图案化掩模。 通过图案化掩模去除对应于第二区域中的第二栅极的底层以暴露第二栅极，其中对应于第一区域中的第一栅极的底层被部分消耗以暴露第一栅极的部分。