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公开(公告)号:US20220416081A1
公开(公告)日:2022-12-29
申请号:US17902928
申请日:2022-09-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Purakh Raj Verma , Ching-Yang Wen , Li Wang , Kai Cheng
IPC: H01L29/78 , H01L29/66 , H01L29/417 , H01L29/40 , H01L29/06
Abstract: A method of fabricating a semiconductor device is provided. First, a semiconductor structure is provided, and the semiconductor structure includes a buried dielectric layer, a first gate structure disposed on a front-side of the buried dielectric layer, and a first source/drain region and a second source/drain region disposed between the buried dielectric layer and the first gate structure. Then, a trench is formed in the buried dielectric layer. Afterwards, a conductive layer is formed on the buried dielectric layer and in the trench. Finally, the conductive layer is patterned.
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公开(公告)号:US11476363B2
公开(公告)日:2022-10-18
申请号:US17117080
申请日:2020-12-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Purakh Raj Verma , Ching-Yang Wen , Li Wang , Kai Cheng
IPC: H01L29/78 , H01L29/06 , H01L29/66 , H01L29/40 , H01L29/417
Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a trench, and a contact layer. The first gate structure is disposed on a front-side of the buried dielectric layer, and the second gate structure is disposed on a backside of the buried dielectric layer. The first source/drain region and a second source/drain region are disposed between the first gate structure and the second gate structure. The trench is formed in the buried dielectric layer, and the contact layer is disposed in the trench and electrically coupled to the second source/drain region, where the contact structure and the second gate structure are formed of the same material.
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公开(公告)号:US11296023B2
公开(公告)日:2022-04-05
申请号:US17140146
申请日:2021-01-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Purakh Raj Verma , Ching-Yang Wen , Li Wang , Kai Cheng
IPC: H01L21/00 , H01L23/522 , H01L27/12 , H01L21/768 , H01L29/423 , H01L29/417
Abstract: A semiconductor device comprises a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a front-side metallization, a backside metallization, and conductive contacts. The first gate structure and the second gate structure disposed respectively in the front-side and back side of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structures. The front-side metallization is disposed on the front-side of the buried dielectric layer, and the backside metallization is disposed on the backside of the buried dielectric layer. The conductive contacts penetrate the buried dielectric layer and electrically couple the front-side metallization to the backside metallization.
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公开(公告)号:US20200328311A1
公开(公告)日:2020-10-15
申请号:US16408415
申请日:2019-05-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Purakh Raj Verma , Ching-Yang Wen , Li Wang , Kai Cheng
IPC: H01L29/786 , H01L29/06 , H01L29/78 , H01L29/768
Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.
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公开(公告)号:US11881529B2
公开(公告)日:2024-01-23
申请号:US17902928
申请日:2022-09-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Purakh Raj Verma , Ching-Yang Wen , Li Wang , Kai Cheng
CPC classification number: H01L29/7838 , H01L29/0649 , H01L29/401 , H01L29/41725 , H01L29/66484 , H01L29/7831
Abstract: A method of fabricating a semiconductor device is provided. First, a semiconductor structure is provided, and the semiconductor structure includes a buried dielectric layer, a first gate structure disposed on a front-side of the buried dielectric layer, and a first source/drain region and a second source/drain region disposed between the buried dielectric layer and the first gate structure. Then, a trench is formed in the buried dielectric layer. Afterwards, a conductive layer is formed on the buried dielectric layer and in the trench. Finally, the conductive layer is patterned.
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公开(公告)号:US20210125921A1
公开(公告)日:2021-04-29
申请号:US17140146
申请日:2021-01-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Purakh Raj Verma , Ching-Yang Wen , Li Wang , Kai Cheng
IPC: H01L23/522 , H01L27/12 , H01L29/417 , H01L29/423 , H01L21/768
Abstract: A semiconductor device comprises a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a front-side metallization, a backside metallization, and conductive contacts. The first gate structure and the second gate structure disposed respectively in the front-side and back side of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structures. The front-side metallization is disposed on the front-side of the buried dielectric layer, and the backside metallization is disposed on the backside of the buried dielectric layer. The conductive contacts penetrate the buried dielectric layer and electrically couple the front-side metallization to the backside metallization.
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公开(公告)号:US10923599B2
公开(公告)日:2021-02-16
申请号:US16408415
申请日:2019-05-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Purakh Raj Verma , Ching-Yang Wen , Li Wang , Kai Cheng
IPC: H01L29/786 , H01L29/06 , H01L29/768 , H01L29/78
Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.
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公开(公告)号:US20210098624A1
公开(公告)日:2021-04-01
申请号:US17117080
申请日:2020-12-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Purakh Raj Verma , Ching-Yang Wen , Li Wang , Kai Cheng
IPC: H01L29/78 , H01L29/06 , H01L29/417 , H01L29/40 , H01L29/66
Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a trench, and a contact layer. The first gate structure is disposed on a front-side of the buried dielectric layer, and the second gate structure is disposed on a backside of the buried dielectric layer. The first source/drain region and a second source/drain region are disposed between the first gate structure and the second gate structure. The trench is formed in the buried dielectric layer, and the contact layer is disposed in the trench and electrically coupled to the second source/drain region, where the contact structure and the second gate structure are formed of the same material.
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