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公开(公告)号：US11631679B2
公开(公告)日：2023-04-18
申请号：US17741431
申请日：2022-05-10
Inventor： Luo-Hsin Lee , Ting-Pang Chung , Shih-Han Hung , Po-Han Wu , Shu-Yen Chan , Shih-Fang Tzou
IPC: H01L27/108 , H01L49/02
Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
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公开(公告)号：US20190181141A1
公开(公告)日：2019-06-13
申请号：US16175851
申请日：2018-10-31
Inventor： Luo-Hsin Lee , Ting-Pang Chung , Shih-Han Hung , Po-Han Wu , Shu-Yen Chan , Shih-Fang Tzou
IPC: H01L27/108 , H01L49/02
Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench
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公开(公告)号：US10777559B1
公开(公告)日：2020-09-15
申请号：US16361222
申请日：2019-03-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Han Wu , Feng-Yi Chang , Fu-Che Lee , Wen-Chieh Lu
IPC: H01L27/108
Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.
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公开(公告)号：US10529719B2
公开(公告)日：2020-01-07
申请号：US15961827
申请日：2018-04-24
Inventor： Po-Han Wu , Li-Wei Feng , Shih-Han Hung , Fu-Che Lee , Chien-Cheng Tsai
IPC: H01L27/108 , H01L21/768
Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
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公开(公告)号：US20190296019A1
公开(公告)日：2019-09-26
申请号：US15961827
申请日：2018-04-24
Inventor： Po-Han Wu , Li-Wei Feng , Shih-Han Hung , Fu-Che Lee , Chien-Cheng Tsai
IPC: H01L27/108 , H01L21/768
Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
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Patent Agency Ranking
公开(公告)号：US11770924B2
公开(公告)日：2023-09-26
申请号：US18106448
申请日：2023-02-06
Inventor： Luo-Hsin Lee , Ting-Pang Chung , Shih-Han Hung , Po-Han Wu , Shu-Yen Chan , Shih-Fang Tzou
CPC classification number: H10B12/0387 , H01L28/60 , H10B12/0335 , H10B12/37 , H10B12/315
Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
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公开(公告)号：US20220271037A1
公开(公告)日：2022-08-25
申请号：US17741431
申请日：2022-05-10
Inventor： Luo-Hsin Lee , Ting-Pang Chung , Shih-Han Hung , Po-Han Wu , Shu-Yen Chan , Shih-Fang Tzou
IPC: H01L27/108 , H01L49/02
Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
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公开(公告)号：US10475794B1
公开(公告)日：2019-11-12
申请号：US16026069
申请日：2018-07-03
Inventor： Po-Han Wu , Fu-Che Lee , Chien-Cheng Tsai , Tzu-Tsen Liu , Wen-Chieh Lu
IPC: H01L27/108 , H01L21/762
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first bit line structure on a substrate; forming a first spacer adjacent to the first bit line structure; forming an interlayer dielectric (ILD) layer adjacent to the first spacer; removing part of the ILD layer and part of the first spacer to expose a sidewall of the first bit line structure; and forming a first storage node contact isolation structure adjacent to the first bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure and the first spacer directly.
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公开(公告)号：US20230189498A1
公开(公告)日：2023-06-15
申请号：US18106448
申请日：2023-02-06
Inventor： Luo-Hsin Lee , Ting-Pang Chung , Shih-Han Hung , Po-Han Wu , Shu-Yen Chan , Shih-Fang Tzou
IPC: H10B12/00
CPC classification number: H10B12/0387 , H01L28/60 , H10B12/37 , H10B12/0335 , H10B12/315
Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.
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公开(公告)号：US11233057B2
公开(公告)日：2022-01-25
申请号：US16699756
申请日：2019-12-02
Inventor： Po-Han Wu , Li-Wei Feng , Shih-Han Hung , Fu-Che Lee , Chien-Cheng Tsai
IPC: H01L27/108 , H01L21/768
Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
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