公开(公告)号：US20200119027A1

公开(公告)日：2020-04-16

申请号：US16177812

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANG XIANG ,  CHIA-CHING HSU ,  CHUN-SUNG HUANG ,  YUNG-LIN TSENG ,  WEI-CHANG LIU ,  SHEN-DE WANG

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.