公开(公告)号：US07912693B1

公开(公告)日：2011-03-22

申请号：US12113363

申请日：2008-05-01

申请人： Ui Sun Han ,  Walter N. Sze ,  Tsu-Chien Shen

发明人： Ui Sun Han ,  Walter N. Sze ,  Tsu-Chien Shen

IPC分类号： G06F17/50 ,  G06F9/00

CPC分类号： G06F17/5022 ,  G06F17/5027

摘要： Systems and methods are provided for verifying respective configuration data values for programming configuration memory cells of an integrated circuit device such as a programmable logic device (PLD). Each configuration memory cell controls an input of a corresponding initialization value from a file in response to a selectable assertion of an initialization signal of a test bench during a logic simulation of the PLD. The file structurally associates the configuration memory cell with the corresponding initialization value. A current value of one or more of the configuration memory cells is written with the respective configuration data value via a configuration port of the PLD during the logic simulation. Each configuration memory cell compares its initialization and current values in response to a selectable assertion of a check signal of the test bench. A mismatch error is output in response to a difference between the initialization and current values of one or more of the configuration memory cells.

摘要翻译： 提供了用于验证用于编程诸如可编程逻辑器件（PLD）的集成电路器件的配置存储器单元的相应配置数据值的系统和方法。 响应于在PLD的逻辑模拟期间对测试台的初始化信号的选择性断言，每个配置存储单元控制来自文件的相应初始化值的输入。 该文件结构地将配置存储单元与相应的初始化值相关联。 在逻辑模拟期间，通过PLD的配置端口，通过相应的配置数据值写入一个或多个配置存储器单元的当前值。 每个配置存储器单元响应于可选择地确定测试台的检查信号来比较其初始化和当前值。 响应于一个或多个配置存储器单元的初始化和当前值之间的差异而输出不匹配错误。