公开(公告)号：US20240334675A1

公开(公告)日：2024-10-03

申请号：US18616472

申请日：2024-03-26

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Koji SAKUI ,  Yoshihisa Iwata ,  Masakazu Kakumu ,  Nozomu Harada

IPC分类号： H10B12/00 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096

CPC分类号： H10B12/20 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4096

摘要： In a memory device, a page is composed of memory cells arranged in rows, and pages are arranged in columns in plan view on a substrate. Each memory cell has a semiconductor base, a first impurity region and a second impurity region at both ends of the semiconductor base, and at least two gate conductor layers. The first impurity region is connected to a source line, the second impurity region to a bit line, one of the two gate conductor layers to a selection gate line, and the other to a plate line. Voltages applied to these lines are controlled to perform page erasing and writing operations. A hole group formed by impact ionization is retained within the semiconductor base to have three-valued logic storage data. A sense amplifier circuit performs determination in an order of logic storage data with a large number of holes in the hole group.