公开(公告)号：US11909401B2

公开(公告)日：2024-02-20

申请号：US17766689

申请日：2020-10-09

Applicant: University of Washington

Inventor： Samrat Dey ,  Thomas Lewellen ,  Jacques Christophe Rudell

IPC: H03K5/00 ,  H03K5/24 ,  H03K19/20

CPC classification number: H03K5/24 ,  H03K5/2427 ,  H03K19/20

Abstract: An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT−) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT− signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.

公开(公告)号：US20230336168A1

公开(公告)日：2023-10-19

申请号：US17766689

申请日：2020-10-09

Applicant: Thomas Lewellen ,  University of Washington

Inventor： Samrat Dey ,  Thomas Lewellen ,  Jacques Christophe Rudell

IPC: H03K5/24

CPC classification number: H03K5/24 ,  H03K19/20

Abstract: An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT−) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT− signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.