公开(公告)号：US08572299B2

公开(公告)日：2013-10-29

申请号：US13251323

申请日：2011-10-03

申请人： Uwe Pross ,  Tobias Weber ,  Gunnar Nitsche ,  Thomas Fliess

发明人： Uwe Pross ,  Tobias Weber ,  Gunnar Nitsche ,  Thomas Fliess

IPC分类号： G06F5/00 ,  G06T1/00

CPC分类号： G06F9/3881

摘要： A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.

摘要翻译： 硬件加速器模块由系统处理器经由系统总线驱动，以便根据由处理器定义的参数集来顺序地处理数据流的数据块。 模块包括适于从系统处理器接收参数集的寄存器块，适于接收流数据的加速器核心，以由参数集定义的方式处理所述流数据的数据块，以及输出处理后的流数据，以及 参数缓冲块，其适于连续地存储多个参数集，并且作为硬件加速器核心的忙状态的函数，将参数集顺序地提供给硬件加速器核心。 参数缓冲块可以减少硬件加速器的停机时间，增加数据吞吐量，并降低驱动多个硬件加速器的处理器中处理器过载的风险。