公开(公告)号：US08687681B2

公开(公告)日：2014-04-01

申请号：US13861216

申请日：2013-04-11

Applicant: VIA Technologies, Inc.

Inventor： Chin-Fa Hsiao ,  Shih-Min Lin

IPC: H04B3/46 ,  H04B17/00 ,  H04Q1/20

CPC classification number: H04L7/0079 ,  H04B17/0085

Abstract: A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same.

Abstract translation: 接收机包括CDR电路，串并转换器和测试模块。 CDR电路用于接收串联输入的测试信号组，并接收测试信号组的发送频率以获得时钟信号，其中时钟信号用于提供接收机的工作频率。 串并转换器用于接收由CDR电路输出的测试信号组，并将串行输入的测试信号组转换为并行输出的多个测试字节，其中每个测试字节具有多位数据 。 测试模块用于接收测试字节和时钟信号，并比较测试字节的两个相邻字节，以确定两个相邻测试字节是否完全相同。

公开(公告)号：US20130230132A1

公开(公告)日：2013-09-05

申请号：US13861216

申请日：2013-04-11

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Chin-Fa Hsiao ,  Shih-Min Lin

IPC: H04L7/00

CPC classification number: H04L7/0079 ,  H04B17/0085

Abstract: A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same.

Abstract translation: 接收机包括CDR电路，串并转换器和测试模块。 CDR电路用于接收串联输入的测试信号组，并接收测试信号组的发送频率以获得时钟信号，其中时钟信号用于提供接收机的工作频率。 串并转换器用于接收由CDR电路输出的测试信号组，并将串行输入的测试信号组转换为并行输出的多个测试字节，其中每个测试字节具有多位数据 。 测试模块用于接收测试字节和时钟信号，并比较测试字节的两个相邻字节，以确定两个相邻测试字节是否完全相同。