公开(公告)号：US20200097423A1

公开(公告)日：2020-03-26

申请号：US16231420

申请日：2018-12-22

Applicant: VIA Technologies, Inc.

Inventor： Wen-Pin Chiang

IPC: G06F13/28 ,  G06F13/40 ,  G06F15/78

Abstract: An architecture of a multi-core electronic system is provided. The architecture includes a plurality of first computing cores, a first ring bus, a direct memory access (DMA) engine, and a DMA ring controller. The first computing cores are connected to the first ring bus. The DMA ring controller connects the DMA engine to the first ring bus. The first computing cores communicate with the DMA engine through the first ring bus and make the DMA engine perform a memory operation.

公开(公告)号：US10909056B2

公开(公告)日：2021-02-02

申请号：US16231420

申请日：2018-12-22

Applicant: VIA Technologies, Inc.

Inventor： Wen-Pin Chiang

IPC: G06F13/28 ,  G06F15/78 ,  G06F13/40

Abstract: An architecture of a multi-core electronic system is provided. The architecture includes a plurality of first computing cores, a first ring bus, a direct memory access (DMA) engine, and a DMA ring controller. The first computing cores are connected to the first ring bus. The DMA ring controller connects the DMA engine to the first ring bus. The first computing cores communicate with the DMA engine through the first ring bus and make the DMA engine perform a memory operation.