Dual-structure acquisition circuit for frequency synthesis

    公开(公告)号:US11626882B1

    公开(公告)日:2023-04-11

    申请号:US17750792

    申请日:2022-05-23

    摘要: A wide band frequency synthesizer may include a primary phase-locked loop (PLL) to receive a signal that include a local signal and a VCO signal mixed together and to generate the tuning voltage based on a phase comparison of the local signal and the VCO signal. The local signal may be obtained from a reference signal through frequency multiplication. If the primary PLL fails to lock onto an output frequency, a secondary PLL (acquisition circuit) may be switched in performing a phase comparison between the reference signal and the VCO signal to generate the tuning voltage. The secondary PLL may then provide the tuning voltage to an output of the primary PLL.

    PROCESSING A BEAMFORMED RADIO FREQUENCY (RF) SIGNAL

    公开(公告)号:US20200186267A1

    公开(公告)日:2020-06-11

    申请号:US16786074

    申请日:2020-02-10

    摘要: A device may receive a beamformed wireless signal from a base station. The device may perform a frequency conversion of the beamformed wireless signal to form a frequency converted signal after receiving the beamformed wireless signal. The device may perform, after performing the frequency conversion, processing related to at least one of: analyzing the frequency converted signal, scanning a channel associated with the frequency converted signal, or generating a map related to the frequency converted signal. The device may generate, after performing the processing, output related to at least one of: the analyzing the frequency converted signal, the scanning the channel, or the generating the map.