专利检索 ap:("Valeria Mihalache" OR "Christopher H. Kingsley" OR "Jimmy Z. Wang" OR "Kumar Deepak") AND inv:"Jimmy Z. Wang" 第 1 页

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发明授权
Scheduling processes in simulation of a circuit design based on simulation costs and runtime states of HDL processes 有权
标题翻译：基于HDL过程的仿真成本和运行时状态的电路设计仿真中的调度过程

公开(公告)号：US08768678B1

公开(公告)日：2014-07-01

申请号：US13245174

申请日：2011-09-26

申请人： Valeria Mihalache , Christopher H. Kingsley , Jimmy Z. Wang , Kumar Deepak

发明人： Valeria Mihalache , Christopher H. Kingsley , Jimmy Z. Wang , Kumar Deepak

IPC分类号： G06F9/45 , G06F9/455 , G06F17/00

CPC分类号： G06F9/4881 , G06F17/5009

摘要： One or more embodiments provide a load balancing solution for improving the runtime performance of parallel HDL simulators. During compilation each process is analyzed to determine a simulation cost based on complexity of the HDL processes. During simulation, processes to be executed in the same simulation cycle are scheduled using the simulation costs computed at compile-time in order to reduce the delay incurred during simulation.

摘要翻译： 一个或多个实施例提供用于改善并行HDL模拟器的运行时性能的负载平衡解决方案。在编译期间，分析每个过程以基于HDL过程的复杂度来确定模拟成本。在仿真期间，使用在编译时计算的仿真成本来调度在相同模拟周期中执行的过程，以减少模拟期间产生的延迟。