公开(公告)号：US06763504B2

公开(公告)日：2004-07-13

申请号：US10237328

申请日：2002-09-06

申请人： Vasant B. Rao ,  Ravichander Ledalla ,  Jeffrey P. Soreff ,  Fred L. Yang

发明人： Vasant B. Rao ,  Ravichander Ledalla ,  Jeffrey P. Soreff ,  Fred L. Yang

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor. It also preserves the delays at all nodes in the interconnect network apart from the two ends of the resistor selected for shorting.

摘要翻译： 描述了在内部节点消除之后进一步减少互连网络中的RC寄生效应的方法。 最初选择一个电阻作为短路的候选，并且确定电阻器两端的累积延迟误差是否小于预定阈值。 该阈值必须是通过内部节点消除技术选择的时间常数阈值的一小部分，以便限制累积延迟误差的增长。 本发明的一个重要方面是用于改变下游电阻值的公式的简单性，即，电阻器的值的乘积与电阻器的两端的累积下游电容的比值，其值为 改变了 更新下游电阻值的这一特定选择可以使由于所选择的电阻器的短路导致的每个节点的延迟误差的绝对值最小化。 它还保留互连网络中所有节点之间的延迟，除了选择短路的电阻器的两端之外。