公开(公告)号：US08219961B2

公开(公告)日：2012-07-10

申请号：US13112837

申请日：2011-05-20

申请人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

IPC分类号： G06F9/455 ,  G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.

摘要翻译： 用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。 该方法的第一步是从阵列中选择一个用于分析的晶体管。 该方法根据需要在阵列的晶体管之间循环。 接下来分析所选晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定由布局邻域引起的驱动电流变化。 该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。 该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

公开(公告)号：US07949985B2

公开(公告)日：2011-05-24

申请号：US11757338

申请日：2007-06-01

申请人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

IPC分类号： G06F9/455 ,  G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.

摘要翻译： 用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。 该方法的第一步是从阵列中选择一个用于分析的晶体管。 该方法根据需要在阵列的晶体管之间循环。 接下来分析所选择的晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定由布局邻域引起的驱动电流变化。 该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。 该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

公开(公告)号：US20110219351A1

公开(公告)日：2011-09-08

申请号：US13112837

申请日：2011-05-20

申请人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.

摘要翻译： 用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。 该方法的第一步是从阵列中选择一个用于分析的晶体管。 该方法根据需要在阵列的晶体管之间循环。 接下来分析所选择的晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定由布局邻域引起的驱动电流变化。 该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。 该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

公开(公告)号：US20080297237A1

公开(公告)日：2008-12-04

申请号：US11757338

申请日：2007-06-01

申请人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

发明人： Victor Moroz ,  Dipankar Pramanik ,  Kishore Singhal ,  Xi-Wei Lin

IPC分类号： G05F3/02

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.

摘要翻译： 用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。 该方法的第一步是从阵列中选择一个用于分析的晶体管。 该方法根据需要在阵列的晶体管之间循环。 接下来分析所选择的晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定由布局邻域引起的驱动电流变化。 该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。 该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

公开(公告)号：US07587691B2

公开(公告)日：2009-09-08

申请号：US11599145

申请日：2006-11-14

申请人： Edhi Sutjahjo ,  Kishore Singhal ,  Byungwook Kim ,  Goetz Leonhardt ,  Beifang Qiu ,  Sergey Krasnovsky ,  Baribrata Biswas ,  Alex Gyure ,  Mahmoud Shahram

发明人： Edhi Sutjahjo ,  Kishore Singhal ,  Byungwook Kim ,  Goetz Leonhardt ,  Beifang Qiu ,  Sergey Krasnovsky ,  Baribrata Biswas ,  Alex Gyure ,  Mahmoud Shahram

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5018 ,  G06F2217/10 ,  G06F2217/78

摘要： One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which includes nominal parameter values for a first interconnect layer, and parameter-variation values which represent variations in the nominal parameter values due to random process variations. Next, the system receives an interconnect template which describes the geometry of a portion of a second interconnect layer. The system then determines electrical property data for the interconnect template using the interconnect technology data. The electrical property data can include a nominal electrical property value, and sensitivity values which represent the sensitivities of the nominal electrical property value to variations in the nominal parameter values. Next, the system stores the electrical property data and the interconnect technology data in a storage.

摘要翻译： 本发明的一个实施例提供一种用于确定互连层的电性能的系统。 在操作期间，系统接收包括第一互连层的标称参数值的互连技术数据，以及表示随机过程变化引起的标称参数值变化的参数变化值。 接下来，系统接收描述第二互连层的一部分的几何形状的互连模板。 然后，系统使用互连技术数据确定互连模板的电性能数据。 电性能数据可以包括标称电特性值，以及表示标称电特性值对标称参数值变化的灵敏度的灵敏度值。 接下来，系统将电气特性数据和互连技术数据存储在存储器中。