公开(公告)号：US07020856B2

公开(公告)日：2006-03-28

申请号：US10389316

申请日：2003-03-14

申请人： Vigyan Singhal ,  Joseph E. Higgins

发明人： Vigyan Singhal ,  Joseph E. Higgins

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： Methodology for verifying properties of a circuit model in context of given environmental constraints is disclosed. Verification of a specified property is performed by analyzing only a portion of the circuit model. The present methodology is also directed towards reducing the computation time for verifying the specified property. Further, the present methodology allows the connection of an additional circuit model to the circuit model in a non-intrusive manner. The connection is made without making any modifications to the description of the circuit model. This permits the straightforward specification of related environmental constraints and properties, which makes it possible to verify correct behavior of complex interfaces.

公开(公告)号：US07137078B2

公开(公告)日：2006-11-14

申请号：US10401315

申请日：2003-03-27

申请人： Vigyan Singhal ,  Joseph E. Higgins ,  Alok N. Singh

发明人： Vigyan Singhal ,  Joseph E. Higgins ,  Alok N. Singh

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/505

摘要： A highlighting system for use with electronic circuit design tools is provided for displaying signal waveforms and Register Transfer Logic (RTL) source code portions corresponding to a selected signal in the same window. The user selects a time and signal to be explored. Based on the selected time and signal, the values of all related signals are identified from a database generated by simulation of RTL source code. Nodes corresponding to the related signals are identified from a gate-level netlist corresponding to the RTL source code and the nodes responsible for the particular value of the selected signal at selected time are identified. The nodes are then mapped on to the RTL source code portions by a process of Instrumentation. The RTL source code portions so identified are then displayed. In particular, the portions of the RTL source code responsible for the particular value or transition in particular value of the signal at the selected time are highlighted.

摘要翻译： 提供了一种用于电子电路设计工具的突出显示系统，用于在同一窗口中显示对应于选定信号的信号波形和寄存器传输逻辑（RTL）源代码部分。 用户选择要探索的时间和信号。 根据所选择的时间和信号，从通过RTL源代码的仿真生成的数据库中识别所有相关信号的值。 从对应于RTL源代码的门级网表识别对应于相关信号的节点，并且识别在选定时间负责所选信号的特定值的节点。 然后通过Instrumentation的过程将节点映射到RTL源代码部分。 然后显示如此识别的RTL源代码部分。 特别地，突出显示负责特定值或在选定时间的信号的特定值转换的RTL源代码的部分。

公开(公告)号：US07065726B1

公开(公告)日：2006-06-20

申请号：US10606419

申请日：2003-06-26

申请人： Vigyan Singhal ,  Joseph E. Higgins ,  Chung-Wah Norris Ip ,  Howard Wong-Toi

发明人： Vigyan Singhal ,  Joseph E. Higgins ,  Chung-Wah Norris Ip ,  Howard Wong-Toi

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： The present invention is used for guiding formal verification of a circuit design in circuit simulation software to optimize the time required for verification of a circuit design. The invention modifies the analysis region being used for verification in order to optimize the time for verification. The invention allows for manual, semi-automatic, and automatic modification of the analysis region. The modification is done by either expanding or reducing the analysis region or by adding new rules as assumptions to the existing analysis region. The invention also uses the concept of an articulation point for modification of the analysis region. The modification of the analysis region is performed in a manner to optimize time and memory required for verification of the circuit design.

摘要翻译： 本发明用于指导电路仿真软件中电路设计的形式验证，以优化电路设计验证所需的时间。 本发明修改了用于验证的分析区域，以优化验证时间。 本发明允许分析区域的手动，半自动和自动修改。 修改是通过扩展或减少分析区域或通过添加新规则作为现有分析区域的假设来完成的。 本发明还使用用于修改分析区域的关节点的概念。 分析区域的修改以优化验证电路设计所需的时间和存储器的方式来执行。

公开(公告)号：US06993730B1

公开(公告)日：2006-01-31

申请号：US09758524

申请日：2001-01-10

申请人： Joseph E. Higgins ,  Vigyan Singhal ,  Adnan Aziz

发明人： Joseph E. Higgins ,  Vigyan Singhal ,  Adnan Aziz

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/504

摘要： This invention determines whether two circuit models have equivalent functionality. The method allows very fast comparison between two circuits taking advantage of previous work done. Whenever an apparatus associated with the method solves a problem, it stores information that learned during the solution of the problem, in a database. If the apparatus is presented with a new problem of determining equivalence between two portions of two circuits, it checks if it has seen sub-circuits similar to either of the two pieces before. If it has, it uses the knowledge cached during the previous checks to make the new check easier. Checking equivalence of two circuit models involves checking equivalence of many pairs of sub-parts. Even when the subsequent comparisons involve different circuits, it is possible to take advantage of the information acquired during previous equivalence checks.

摘要翻译： 本发明确定两个电路模型是否具有相同的功能。 该方法允许利用先前工作完成的两个电路之间的非常快速的比较。 每当与该方法相关联的装置解决问题时，它将在解决问题期间学习的信息存储在数据库中。 如果设备呈现出确定两个电路两部分之间的等效性的新问题，则检查它是否已经看到类似于之前的两个部分之一的子电路。 如果有的话，它会使用先前检查过程中缓存的知识来使新检查变得更容易。 检查两个电路模型的等效性涉及检查多对子部件的等效性。 即使随后的比较涉及不同的电路，也可以利用在先前的等价检查期间获得的信息。

公开(公告)号：US06611947B1

公开(公告)日：2003-08-26

申请号：US09644767

申请日：2000-08-23

申请人： Joseph E. Higgins ,  Vigyan Singhal ,  Adnan Aziz

发明人： Joseph E. Higgins ,  Vigyan Singhal ,  Adnan Aziz

IPC分类号： G06F1750

CPC分类号： G06F17/504

摘要： This invention determines whether two logic level circuit models have equivalent functionality. The method allows difficult portions of the equivalent functionality check to be partitioned and concurrently solved in a distributed computing environment. This permits the user to use, in a scalable fashion, additional computing resources to rapidly solve difficult equivalent functionality checks. The method allows difficult checks to be solved using (1) a divide-and-conquer approach, (2) by a competitive approach in which many independent attempts are made to solve the same check, or (3) by allocating more resources to solve the difficult check.

摘要翻译： 本发明确定两个逻辑电平电路模型是否具有相同的功能。 该方法允许等同功能检查的困难部分在分布式计算环境中进行分区并同时解决。 这允许用户以可扩展的方式使用额外的计算资源来快速地解决困难的等效功能检查。 该方法允许使用（1）分治方法来解决困难的检查，（2）通过竞争方法，其中许多独立尝试来解决相同的检查，或者（3）通过分配更多的资源来解决 困难的检查。