公开(公告)号：US20080270963A1

公开(公告)日：2008-10-30

申请号：US12166811

申请日：2008-07-02

申请人： Vikas Agarwal ,  Michael Ju Hyeok Lee ,  Philip G. Shephard

发明人： Vikas Agarwal ,  Michael Ju Hyeok Lee ,  Philip G. Shephard

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.

摘要翻译： 通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的系统和计算机程序减少了完整设计验证所需的计算时间。 阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。 如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。 观察到字线到达以确定最坏情况行进行选择。 对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。 对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。