Systems and method for spur supression in a multiple radio SoC
    1.
    发明授权
    Systems and method for spur supression in a multiple radio SoC 有权
    多重无线电SoC中的支路抑制系统和方法

    公开(公告)号:US08750805B2

    公开(公告)日:2014-06-10

    申请号:US12969800

    申请日:2010-12-16

    IPC分类号: H04B1/00

    CPC分类号: H03K3/017 H04B2215/067

    摘要: A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed.

    摘要翻译: 数字系统包括一个辅助计算器,其计算数字时钟信号的频率的谐波,并且识别位于射频电路的操作频带中的谐波。 占空比计算模块接收谐波并计算谐波的占空比。 此外,耦合到占空比计算块的时钟发生器产生频率和占空比的数字时钟信号,从而抑制由谐波引起的杂散振幅。

    SYSTEMS AND METHOD FOR SPUR SUPRESSION IN A MULTIPLE RADIO SoC
    2.
    发明申请
    SYSTEMS AND METHOD FOR SPUR SUPRESSION IN A MULTIPLE RADIO SoC 有权
    用于在多个无线电SoC中进行表情的系统和方法

    公开(公告)号:US20120154010A1

    公开(公告)日:2012-06-21

    申请号:US12969800

    申请日:2010-12-16

    IPC分类号: H03K3/00

    CPC分类号: H03K3/017 H04B2215/067

    摘要: A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed.

    摘要翻译: 数字系统包括一个辅助计算器,其计算数字时钟信号的频率的谐波,并且识别位于射频电路的操作频带中的谐波。 占空比计算模块接收谐波并计算谐波的占空比。 此外,耦合到占空比计算块的时钟发生器产生频率和占空比的数字时钟信号,从而抑制由谐波引起的杂散振幅。