公开(公告)号：US3728679A

公开(公告)日：1973-04-17

申请号：US3728679D

申请日：1971-10-21

Applicant: WESTON INSTRUMENTS INC

Inventor： MC INTOSH B

IPC: G06K7/015 ,  G11B20/20 ,  G06K5/04

CPC classification number: G11B20/20 ,  G06K7/015

Abstract: A device for correcting the time relationship of parallel data bits to eliminate the effect of certain forms of static skew. The apparatus accepts the data bits on parallel channels, one of which is arbitrarily designated as the ''''master channel,'''' the others being slave channels. Logic associated with the master channel generates an early gate signal upon arrival of a master channel data bit, and a late gate signal is generated, also as a result of the data bit arrival. An interval between the early gate and the late gate defines a ''''window'''' in time within which the apparatus produces a master channel data bit out, delayed by a predetermined amount, and within which the slave channel data bits should occur. If the slave channel data bits do not occur within this window, delay means in each slave channel is altered to readjust the occurence of the data bit out. Each slave channel is adjusted individually in accordance with the gate signal so that, after cyclic adjustment, the data bits are in essential coincidence. The interval between the early and late gate is adjustable by a sensitivity control to determine the accuracy of coincidence desired.

Abstract translation: 用于校正并行数据位的时间关系以消除某些形式的静态偏移的影响的装置。 该装置接受并行信道上的数据位，其中一个被任意指定为“主信道”，其他信道是从信道。 与主通道相关联的逻辑在主通道数据位到达时产生早期门信号，并且还产生后门信号，也是数据位到达的结果。 早期门和后门之间的间隔在时间上定义了“窗口”，在该窗口内设备产生主通道数据位输出，延迟预定量，并且在其中应发生从通道数据位。 如果在该窗口内没有发生从属通道数据位，则更改每个从通道中的延迟装置，以便重新调整数据位的出现位。 每个从通道根据门信号单独调整，使得在循环调整之后，数据位是必不可少的。 早期和晚期门之间的间隔可以通过灵敏度控制来调节，以确定所需的重合精度。