SCALABLE SCHEDULER ARCHITECTURE FOR CHANNEL DECODING
    1.
    发明申请
    SCALABLE SCHEDULER ARCHITECTURE FOR CHANNEL DECODING 审中-公开
    用于信道解码的可调度调度器架构

    公开(公告)号:US20110280133A1

    公开(公告)日:2011-11-17

    申请号:US13104844

    申请日:2011-05-10

    IPC分类号: H04W72/04 H04W24/00

    CPC分类号: H04L1/0052

    摘要: Certain aspects of the present disclosure relate to a method for processing wireless communications. According to one aspect, a processing unit may receive a plurality of code blocks of a transport block and schedule the plurality of code blocks to be decoded in parallel with a plurality of decoders. Each decoder decodes at least one code block as an independent tasks. The processing unit further collects the decoded information bits from the plurality of decoders and forwards the collected decoded information bits for further processing. In one aspect, the processing unit includes an output agent to temporarily store the decoded information bits while waiting for all code blocks of the transport block to be decoded.

    摘要翻译: 本公开的某些方面涉及一种用于处理无线通信的方法。 根据一个方面,处理单元可以接收传输块的多个码块,并且与多个解码器并行地调度要解码的多个码块。 至少一个解码器解码至少一个代码块作为独立任务。 处理单元进一步从多个解码器中收集解码的信息比特,并且转发所收集的解码信息比特用于进一步处理。 一方面,处理单元包括一个输出代理,用于临时存储解码的信息位,同时等待传输块的所有代码块被解码。