公开(公告)号：US08156466B2

公开(公告)日：2012-04-10

申请号：US12340234

申请日：2008-12-19

申请人： Weiqing Guo ,  Sandeep Bhutani

发明人： Weiqing Guo ,  Sandeep Bhutani

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

摘要翻译： 用于VLSI电路的互连延迟分析的改进方法通过消除图中的一个或多个节点来减少用于时刻计算的寄生图。 基于节点的程度来执行消除处理。 通过以这种方式消除节点，显着地减少了计算复杂度。 通过这种消除过程，电阻环和交叉环也可以解决。 使用寄生图上的深度优先搜索方法优化消除节点的顺序，进一步降低计算复杂度。 该方法提供了一致的功能接口，适用于不同的电路模型结构。 此外，该方法考虑了互连之间的耦合电容。

公开(公告)号：US07661083B2

公开(公告)日：2010-02-09

申请号：US12046169

申请日：2008-03-11

申请人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

发明人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

摘要翻译： 一种确定来自侵略者网络的电压是否超过集成电路设计中的受害网络设计的电压阈值的方法。 计算受害者网络上侵略者网络的概率噪声。 根据电压阈值检查概率噪声，当概率噪声不超过电压阈值时，通过受害网设计。 当概率噪声超过阈值时，计算所需的故障平均时间的有效噪声，并根据电压阈值检查有效噪声。 当有效噪声不超过电压阈值时，受害者网络设计通过，当有效噪声超过阈值时失败。

公开(公告)号：US20050251354A1

公开(公告)日：2005-11-10

申请号：US10842879

申请日：2004-05-10

申请人： Weiqing Guo ,  Sandeep Bhutani ,  Oian Cui

发明人： Weiqing Guo ,  Sandeep Bhutani ,  Oian Cui

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5036

摘要： A method includes steps of: (a) receiving as input a waveform of a transient signal as a function of time for an aggressor net; (b) finding a peak value of the waveform and a corresponding peak time of the waveform propagated from the aggressor net to a victim net; (c) defining a selected time interval within the waveform at the victim net that includes the peak value and excludes features of the waveform not associated with the peak value wherein the selected time interval begins at a first time and ends at a second time; (d) calculating a weighted value of a function of the waveform at the first time and the second time; (e) calculating a local average value of the waveform as a function of the peak value and the weighted value; and (f) generating as output the local average value of the waveform.

摘要翻译： 一种方法包括以下步骤：（a）作为输入接收作为侵入网的时间的函数的瞬态信号的波形; （b）找出波形的峰值和从侵略网传播到受害网的波形的相应峰值时间; （c）在包括峰值的受害网络的波形内定义所选择的时间间隔，并排除与峰值不相关联的波形的特征，其中所选择的时间间隔在第一时间开始并在第二时间结束; （d）计算第一次和第二次的波形的函数的加权值; （e）计算作为峰值和加权值的函数的波形的局部平均值; 和（f）产生波形的局部平均值作为输出。

公开(公告)号：US07334204B2

公开(公告)日：2008-02-19

申请号：US11324082

申请日：2005-12-29

申请人： Weiqing Guo ,  Sandeep Bhutani ,  Ivan Pavisic

发明人： Weiqing Guo ,  Sandeep Bhutani ,  Ivan Pavisic

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; adding a gate delay of each of the inputs to the separate interconnect delay calculated as a function of the input ramptime to estimate a stage delay for each of the inputs; and generating as output the stage delay for each of the inputs.

摘要翻译： 一种用于估计集成电路设计中的级延迟的系统包括以下步骤：接收作为输入的集成电路设计，其包括具有至少两个输入的单级，输出和连接到所述输出的互连; 计算互连的单独互连延迟作为每个输入的输入衰减的函数; 将每个输入的门延迟添加到作为输入衰减时间的函数计算的单独互连延迟，以估计每个输入的级延迟; 并为每个输入产生阶段延迟作为输出。

公开(公告)号：US07082583B2

公开(公告)日：2006-07-25

申请号：US10301069

申请日：2002-11-20

申请人： Weiqing Guo ,  Sandeep Bhutani

发明人： Weiqing Guo ,  Sandeep Bhutani

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

摘要翻译： 用于VLSI电路的互连延迟分析的改进方法通过消除图中的一个或多个节点来减少用于时刻计算的寄生图。 基于节点的程度来执行消除处理。 通过以这种方式消除节点，显着地减少了计算复杂度。 通过这种消除过程，电阻环和交叉环也可以解决。 使用寄生图上的深度优先搜索方法优化消除节点的顺序，进一步降低计算复杂度。 该方法提供了一致的功能接口，适用于不同的电路模型结构。 此外，该方法考虑了互连之间的耦合电容。

公开(公告)号：US06990420B2

公开(公告)日：2006-01-24

申请号：US10842879

申请日：2004-05-10

申请人： Weiqing Guo ,  Sandeep Bhutani ,  Oian Cui

发明人： Weiqing Guo ,  Sandeep Bhutani ,  Oian Cui

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method includes steps of: (a) receiving as input a waveform of a transient signal as a function of time for an aggressor net; (b) finding a peak value of the waveform and a corresponding peak time of the waveform propagated from the aggressor net to a victim net; (c) defining a selected time interval within the waveform at the victim net that includes the peak value and excludes features of the waveform not associated with the peak value wherein the selected time interval begins at a first time and ends at a second time; (d) calculating a weighted value of a function of the waveform at the first time and the second time; (e) calculating a local average value of the waveform as a function of the peak value and the weighted value; and (f) generating as output the local average value of the waveform.

摘要翻译： 一种方法包括以下步骤：（a）作为输入接收作为侵入网的时间的函数的瞬态信号的波形; （b）找出波形的峰值和从侵略网传播到受害网的波形的相应峰值时间; （c）在包括峰值的受害网络的波形内定义选定的时间间隔，并且排除与峰值不相关联的波形的特征，其中所选择的时间间隔在第一时间开始并在第二时间结束; （d）计算第一次和第二次的波形的函数的加权值; （e）计算作为峰值和加权值的函数的波形的局部平均值; 和（f）产生波形的局部平均值作为输出。

公开(公告)号：US07376918B2

公开(公告)日：2008-05-20

申请号：US11079017

申请日：2005-03-11

申请人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

发明人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

摘要翻译： 一种确定来自侵略者网络的电压是否超过集成电路设计中的受害网络设计的电压阈值的方法。 计算受害者网络上侵略者网络的概率噪声。 根据电压阈值检查概率噪声，当概率噪声不超过电压阈值时，通过受害网设计。 当概率噪声超过阈值时，计算所需的故障平均时间的有效噪声，并根据电压阈值检查有效噪声。 当有效噪声不超过电压阈值时，受害者网络设计通过，当有效噪声超过阈值时失败。

公开(公告)号：US20070028199A1

公开(公告)日：2007-02-01

申请号：US11192526

申请日：2005-07-29

申请人： Sandeep Bhutani ,  Qian Cui ,  Weiqing Guo

发明人： Sandeep Bhutani ,  Qian Cui ,  Weiqing Guo

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method of computing output delay in a mathematical model of an integrated circuit original design by sorting cells of the original design in a topological order. The original output delays for the cells in the original design are computed in the sorted order, to produce original output ramp times. The original output ramp times are propagated and original output delays are computed, and the original output ramp time and original output load for each cell is stored. The cells of the original design are modified to produce a modified design. For each modified cell in the topological order, a new output delay and a new output ramp time are computed and compared to the original output ramp time on the modified cell. When the new output ramp time substantially equals the original output ramp time for a modified cell, the calculations of the modified output ramp time for cells that are further down in the topological order are stopped. Otherwise the calculations of the modified output ramp time for cells that are further down in the topological order are continued until a cell is reached where the new output ramp time substantially equals the original output ramp time.

摘要翻译： 一种通过以拓扑顺序排列原始设计的单元来计算集成电路原始设计的数学模型中的输出延迟的方法。 原始设计中的单元的原始输出延迟以排序顺序计算，以产生原始输出斜坡时间。 原始输出斜坡时间被传播并且计算出原始输出延迟，并且存储每个单元的原始输出斜坡时间和原始输出负载。 原始设计的单元被修改以产生修改的设计。 对于每个修改的单元，按拓扑顺序，计算新的输出延迟和新的输出斜坡时间，并将其与修改单元上的原始输出斜坡时间进行比较。 当新的输出斜坡时间基本上等于修改的单元的原始输出斜坡时间时，停止按拓扑顺序进一步降低的单元的修改的输出斜坡时间的计算。 否则，继续按照拓扑顺序进一步降低的单元的修改的输出斜坡时间的计算，直到达到单元，其中新的输出斜坡时间基本上等于原始输出斜坡时间。

公开(公告)号：US20080163145A1

公开(公告)日：2008-07-03

申请号：US12046169

申请日：2008-03-11

申请人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

发明人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

摘要翻译： 一种确定来自侵略者网络的电压是否超过集成电路设计中的受害网络设计的电压阈值的方法。 计算受害者网络上侵略者网络的概率噪声。 根据电压阈值检查概率噪声，当概率噪声不超过电压阈值时，通过受害网设计。 当概率噪声超过阈值时，计算所需的故障平均时间的有效噪声，并根据电压阈值检查有效噪声。 当有效噪声不超过电压阈值时，受害者网络设计通过，当有效噪声超过阈值时失败。

公开(公告)号：US07260801B2

公开(公告)日：2007-08-21

申请号：US11192526

申请日：2005-07-29

申请人： Sandeep Bhutani ,  Qian Cui ,  Weiqing Guo

发明人： Sandeep Bhutani ,  Qian Cui ,  Weiqing Guo

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method of computing output delay in a mathematical model of an integrated circuit by sorting cells of original design of an the integrated circuit in a topological order. The original output delays for the sorted cells in the original design are computed in the topological order, to produce original output ramp times. The original output ramp times are propagated and original output delays are computed, and the original output ramp time and original output load for each cell is stored. The cells of the original design are modified to produce a modified design. For each modified cell in the topological order, a new output delay and a new output ramp time are computed and compared to the original output ramp time on the modified cell. When the new output ramp time substantially equals the original output ramp time for a modified cell, the calculations of the modified output ramp time for cells that are further down in the topological order are stopped. Otherwise the calculations of the modified output ramp time for cells that are further down in the topological order are continued until a cell is reached where the new output ramp time substantially equals the original output ramp time.

摘要翻译： 通过以拓扑顺序对集成电路的原始设计的单元进行排序来计算集成电路的数学模型中的输出延迟的方法。 原始设计中排序单元格的原始输出延迟以拓扑顺序计算，以产生原始输出斜坡时间。 原始输出斜坡时间被传播并且计算出原始输出延迟，并且存储每个单元的原始输出斜坡时间和原始输出负载。 原始设计的单元被修改以产生修改的设计。 对于每个修改的单元，按拓扑顺序，计算新的输出延迟和新的输出斜坡时间，并将其与修改单元上的原始输出斜坡时间进行比较。 当新的输出斜坡时间基本上等于修改的单元的原始输出斜坡时间时，停止按拓扑顺序进一步降低的单元的修改的输出斜坡时间的计算。 否则，继续按照拓扑顺序进一步降低的单元的修改的输出斜坡时间的计算，直到达到单元，其中新的输出斜坡时间基本上等于原始输出斜坡时间。