公开(公告)号：US20120139043A1

公开(公告)日：2012-06-07

申请号：US12957406

申请日：2010-12-01

申请人： Wen-Shin Wu ,  Chun-Yao Huang ,  Hsin-Hua Lin

发明人： Wen-Shin Wu ,  Chun-Yao Huang ,  Hsin-Hua Lin

IPC分类号： H01L29/786

CPC分类号： H01L29/78621 ,  H01L29/7869

摘要： A thin film transistor includes a gate, a pair of electrodes, a first semiconductor layer disposed between the gate and the pair of electrodes, and a semiconductor stacked layer disposed between the first semiconductor layer and the pair of the electrodes. The semiconductor stacked layer includes a second semiconductor layer disposed adjacent to the pair of electrodes and at least one pair of semiconductor layers including a third semiconductor layer and a fourth semiconductor layer, the third semiconductor layer being sandwiched between the second semiconductor layer and the fourth semiconductor layer. In particular, the electric conductivity of the third semiconductor layer is substantially smaller than the electric conductivity of the second semiconductor layer and the electric conductivity of the fourth semiconductor layer.

摘要翻译： 薄膜晶体管包括栅极，一对电极，设置在栅极和一对电极之间的第一半导体层，以及设置在第一半导体层和一对电极之间的半导体层叠层。 半导体堆叠层包括邻近该对电极设置的第二半导体层和包括第三半导体层和第四半导体层的至少一对半导体层，第三半导体层夹在第二半导体层和第四半导体层之间 层。 特别地，第三半导体层的导电率显着小于第二半导体层的导电率和第四半导体层的导电率。

公开(公告)号：US08405085B2

公开(公告)日：2013-03-26

申请号：US12957406

申请日：2010-12-01

申请人： Wen-Shin Wu ,  Chun-Yao Huang ,  Hsin-Hua Lin

发明人： Wen-Shin Wu ,  Chun-Yao Huang ,  Hsin-Hua Lin

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/78621 ,  H01L29/7869

摘要： A thin film transistor includes a gate, a pair of electrodes, a first semiconductor layer disposed between the gate and the pair of electrodes, and a semiconductor stacked layer disposed between the first semiconductor layer and the pair of the electrodes. The semiconductor stacked layer includes a second semiconductor layer disposed adjacent to the pair of electrodes and at least one pair of semiconductor layers including a third semiconductor layer and a fourth semiconductor layer, the third semiconductor layer being sandwiched between the second semiconductor layer and the fourth semiconductor layer. In particular, the electric conductivity of the third semiconductor layer is substantially smaller than the electric conductivity of the second semiconductor layer and the electric conductivity of the fourth semiconductor layer.

摘要翻译： 薄膜晶体管包括栅极，一对电极，设置在栅极和一对电极之间的第一半导体层，以及设置在第一半导体层和一对电极之间的半导体层叠层。 半导体堆叠层包括邻近该对电极设置的第二半导体层和包括第三半导体层和第四半导体层的至少一对半导体层，第三半导体层夹在第二半导体层和第四半导体层之间 层。 特别地，第三半导体层的导电率显着小于第二半导体层的导电率和第四半导体层的导电率。