公开(公告)号：US11989431B2

公开(公告)日：2024-05-21

申请号：US17688384

申请日：2022-03-07

申请人： Western Digital Technologies, Inc.

发明人： Eran Moshe ,  Nava Eisenstein ,  Tomer Baron

IPC分类号： G06F3/06

CPC分类号： G06F3/0635 ,  G06F3/0604 ,  G06F3/0679

摘要： A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store data mappings in an uLayer, where the uLayer includes a plurality of mSet updates, and where the uLayer is organized into a sorted section and an unsorted section, sort one or more of the plurality of mSet updates of the uLayer, and provide, to a host device, data stored in the memory device corresponding to a most recent update of a data mapping by ignoring non-recent updates for a read command associated with an mSet group of the sorted section.

公开(公告)号：US12019878B2

公开(公告)日：2024-06-25

申请号：US17533019

申请日：2021-11-22

申请人： Western Digital Technologies, Inc.

发明人： Nava Eisenstein ,  Jonathan Journo

IPC分类号： G06F3/06 ,  G06F12/1009

CPC分类号： G06F3/0619 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/1009

摘要： A data storage device includes a memory device and a controller. The controller is configured to select a source block, read metadata associated with the source block and compare to a logical block address to physical block address (L2P) table, determine if a flash management unit (FMU) of the source block is valid, and add a new entry associated with the FMU into a valid FMU buffer when the FMU of the source block is determined to be valid. The controller is further configured to determine that the source block has been fully validated and select a next source block based on a valid counter. The valid counter corresponds to an amount of valid data of the next source block.

公开(公告)号：US11604735B1

公开(公告)日：2023-03-14

申请号：US17541028

申请日：2021-12-02

申请人： Western Digital Technologies, Inc.

发明人： Amir Segev ,  Dinesh Kumar Agarwal ,  Vijay Sivasankaran ,  Nava Eisenstein ,  Jonathan Journo

IPC分类号： G06F12/0888 ,  G06F12/0891

摘要： Aspects of a storage device are provided that allow a controller to leverage cache to minimize occurrence of HMB address overlaps between different HMB requests. The storage device may include a cache and a controller coupled to the cache. The controller may store in the cache, in response to a HMB read request, first data from a HMB at a first HMB address. The controller may also store in the cache, in response to an HMB write request, second data from the HMB at a second HMB address. The controller may refrain from processing subsequent HMB requests in response to an overlap of the first HMB address with an address range including the second HMB address, and the controller may resume processing the subsequent HMB requests after the first data is stored. As a result, turnaround time delays for HMB requests may be reduced and performance may be improved.