公开(公告)号：US20240079072A1

公开(公告)日：2024-03-07

申请号：US17902113

申请日：2022-09-02

申请人： Western Digital Technologies, Inc.

发明人： Vishal Sharma ,  Darshan Pagariya ,  Sourabh Sankule

IPC分类号： G11C29/02 ,  G06F3/06

CPC分类号： G11C29/021 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

摘要： A data storage device has a controller that instructs a memory to read memory cells using a number of different read voltage levels and then selects the read voltage level that provides the best read. Instead of sending individual commands for each of the different read voltage levels, the controller sends a single command that specifies an initial read voltage level and a voltage shift, and the memory automatically increments the read voltage level by the voltage shift for each read.

公开(公告)号：US20230205627A1

公开(公告)日：2023-06-29

申请号：US17563533

申请日：2021-12-28

申请人： Western Digital Technologies, Inc.

发明人： Varun Sharma ,  Vishal Sharma ,  Arun Thandapani

IPC分类号： G06F11/10 ,  G06F11/14 ,  G06F11/07 ,  G06F3/06

CPC分类号： G06F11/1068 ,  G06F11/1435 ,  G06F11/0772 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

摘要： A data storage device includes a non-volatile memory and a data storage controller. The data storage controller is configured to generate first XOR parities based on first data of a first metablock of the non-volatile memory and store the first XOR parities in a second metablock of the non-volatile memory. The data storage controller is also configured to generate second XOR parities corresponding to second data of the second metablock. The second data includes two or more XOR parities of the first XOR parities. The data storage controller is further configured to store the second parities in a reserved portion of the first metablock.

公开(公告)号：US11915772B1

公开(公告)日：2024-02-27

申请号：US17902113

申请日：2022-09-02

申请人： Western Digital Technologies, Inc.

发明人： Vishal Sharma ,  Darshan Pagariya ,  Sourabh Sankule

IPC分类号： G11C29/02 ,  G06F3/06

CPC分类号： G11C29/021 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

摘要： A data storage device has a controller that instructs a memory to read memory cells using a number of different read voltage levels and then selects the read voltage level that provides the best read. Instead of sending individual commands for each of the different read voltage levels, the controller sends a single command that specifies an initial read voltage level and a voltage shift, and the memory automatically increments the read voltage level by the voltage shift for each read.

公开(公告)号：US11687409B1

公开(公告)日：2023-06-27

申请号：US17563533

申请日：2021-12-28

申请人： Western Digital Technologies, Inc.

发明人： Varun Sharma ,  Vishal Sharma ,  Arun Thandapani

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F3/06 ,  G06F11/07

CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0772 ,  G06F11/1435

摘要： A data storage device includes a non-volatile memory and a data storage controller. The data storage controller is configured to generate first XOR parities based on first data of a first metablock of the non-volatile memory and store the first XOR parities in a second metablock of the non-volatile memory. The data storage controller is also configured to generate second XOR parities corresponding to second data of the second metablock. The second data includes two or more XOR parities of the first XOR parities. The data storage controller is further configured to store the second parities in a reserved portion of the first metablock.