公开(公告)号：US5101419A

公开(公告)日：1992-03-31

申请号：US510740

申请日：1990-04-18

申请人： William M. Lowe ,  Leland F. Rusk

发明人： William M. Lowe ,  Leland F. Rusk

IPC分类号： H03K5/156

CPC分类号： H03K5/1565

摘要： There is disclosed an improved clock generator responsive to a first clock signal having a frequency f.sub.1 and a second clock signal having a frequency f.sub.2, wherein f.sub.2 is equal to nf.sub.1. The clock generator provides a fixed duty cycle clock signal having a period equal to n complete cycles of the second clock signal and being at a first level for m complete cycles of the second clock signal and a second level for n-m complete cycles of the second clock signal. The clock generator includes a counter for counting half-cycles of the second clock signal to derive the first and second levels, and a flip-flop for establishing a timing condition responsive to the first clock signal. The clock generator further includes an inhibit circuit coupled to the counter for enabling the counter to begin a new counting period in response to the counter counting n complete cycles of the second clock signal and the establishment of the timing condition. The clock generator inhibit circuit guarantees a consistent duty cycle signal output immune to variations of the period of the first clock signal to as low as n-1/2 complete cycles of the second clock signal.

摘要翻译： 公开了一种响应于具有频率f1的第一时钟信号和具有频率f2的第二时钟信号的改进的时钟发生器，其中f2等于nf1。 时钟发生器提供具有等于第二时钟信号的n个完整周期的周期的固定占空比时钟信号，并且在第二时钟信号的m个完整周期处于第一电平，并且在第二时钟的nm个完整周期 信号。 时钟发生器包括用于计数第二时钟信号的半周期以计算第一和第二电平的计数器，以及用于响应于第一时钟信号建立定时条件的触发器。 时钟发生器还包括耦合到计数器的禁止电路，用于使计数器响应于计数器计数第二时钟信号的n个完整周期和建立定时条件而开始新的计数周期。 时钟发生器禁止电路保证一致的占空比信号输出免受第一时钟信号周期的变化，低至第二时钟信号的n-1/2个完整周期。

公开(公告)号：US06383822B1

公开(公告)日：2002-05-07

申请号：US09539099

申请日：2000-03-30

申请人： Michael W. Sprayberry ,  Leland F. Rusk

发明人： Michael W. Sprayberry ,  Leland F. Rusk

IPC分类号： G01R3126

CPC分类号： G01R31/3181

摘要： A testing methodology for increasing the performance and reliability of integrated circuits (“chips”) outputted from a manufacturing process, utilizes a method by which the operating frequency of the integrated circuit is measured when the Self-Timed Pulse Control parameter is adjusted to provide a more strict test upon the chip. Under this more stringent test, the integrated circuits that do not pass the test then are designated as failures or marketed with listed lower operating frequencies.

摘要翻译： 用于提高从制造过程输出的集成电路（“芯片”）的性能和可靠性的测试方法利用了当自定时脉冲控制参数被调整以测量集成电路的工作频率以提供一个 对芯片进行更严格的测试。 在这个更严格的测试下，不通过测试的集成电路被指定为故障，或者列出较低的工作频率。