公开(公告)号：US11088694B1

公开(公告)日：2021-08-10

申请号：US16827409

申请日：2020-03-23

Applicant: X Development LLC

Inventor： Michial Allen Gunter ,  Charles Henry Leichner, IV ,  Tammo Spalink

IPC: G06F15/80 ,  H03K19/17736 ,  H03K19/0175 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06F15/76

Abstract: An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.

公开(公告)号：US10790828B1

公开(公告)日：2020-09-29

申请号：US16042839

申请日：2018-07-23

Applicant: X Development LLC

Inventor： Michial Allen Gunter ,  Charles Henry Leichner, IV ,  Tammo Spalink

IPC: G06F15/80 ,  G06N3/04 ,  H03K19/17736 ,  G06N3/08 ,  G06N3/063 ,  H03K19/0175 ,  G06F15/76

Abstract: An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.