Integrated circuit chip testing interface with reduced signal wires

    公开(公告)号:US11860228B2

    公开(公告)日:2024-01-02

    申请号:US17742363

    申请日:2022-05-11

    Applicant: XILINX, INC.

    CPC classification number: G01R31/318555 G01R31/31727 G01R31/318572

    Abstract: An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.

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