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公开(公告)号:US20210150072A1
公开(公告)日:2021-05-20
申请号:US16686070
申请日:2019-11-15
Applicant: XILINX, INC.
Inventor: Gangadhar Budde , Shreegopal S. Agrawal , Siddharth Rele , Subhojit Deb
IPC: G06F21/76
Abstract: Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the IC can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.
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公开(公告)号:US11188684B2
公开(公告)日:2021-11-30
申请号:US16686070
申请日:2019-11-15
Applicant: XILINX, INC.
Inventor: Gangadhar Budde , Shreegopal S. Agrawal , Siddharth Rele , Subhojit Deb
IPC: G06F21/76
Abstract: Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the IC can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.
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