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    Fractional rate resampling filter on FPGA
    3.
    发明授权
    Fractional rate resampling filter on FPGA 有权
    FPGA上的分数速率重采样滤波器

    公开(公告)号：US08289195B1

    公开(公告)日：2012-10-16

    申请号：US13072592

    申请日：2011-03-25

    申请人： Xiaofei Dong ,  Hong Shan Neoh

    发明人： Xiaofei Dong ,  Hong Shan Neoh

    IPC分类号： H03M7/00

    CPC分类号： H03H17/0292 ,  H03H17/0685 ,  H03H2218/08

    摘要： A programmable logic device can be configured as a fractional rate resampling filter capable of performing downsampling prior to upsampling without modifying the overall filter response. Input data may be received at a first sample rate and may be downsampled to generate downsampled data. Portions of the downsampled data may be respectively output to different filtering paths. Each filtering path may include a cluster of filter components that corresponds to different subfilters of the overall filter response and may be operable to receive and process the different portions of the downsampled data. Outputs of each cluster may be combined to generate output data at a second sample rate. The resampling filter structure can reduce the number of multiplier circuits used by allowing time-division multiplexing among different filter components.

    摘要翻译： 可编程逻辑器件可以配置为分数速率重采样滤波器，其能够在上采样之前执行下采样而不修改整体滤波器响应。 可以以第一采样率接收输入数据，并且可以进行下采样以产生下采样数据。 下采样数据的部分可以分别输出到不同的过滤路径。 每个过滤路径可以包括对应于整个过滤器响应的不同子过滤器的过滤器组件的集群，并且可以用于接收和处理下采样数据的不同部分。 可以组合每个簇的输出以以第二采样率生成输出数据。 重采样滤波器结构可以通过允许不同滤波器组件之间的时分复用来减少所使用的乘法器电路的数量。

    Implementation of multi-channel intermediate frequency modem for radio communication with a programmable integrated circuit
    4.
    发明授权
    Implementation of multi-channel intermediate frequency modem for radio communication with a programmable integrated circuit 有权
    实现与可编程集成电路进行无线通信的多通道中频调制解调器

    公开(公告)号：US08559482B1

    公开(公告)日：2013-10-15

    申请号：US12476129

    申请日：2009-06-01

    申请人： Xiaofei Dong

    发明人： Xiaofei Dong

    IPC分类号： H04B1/00

    CPC分类号： H03H17/065 ,  H03D7/165 ,  H03H17/0286 ,  H03H2218/06

    摘要： Embodiments of the present invention provide methods and systems for implementing a digital up converter (DUC) in an integrated circuit (IC). The method includes serializing a plurality of inputs to obtain a serial output and then increasing the sample rate of the serial output. Additionally, the method generates signal pairs (sine, cosine) for the desired carrier frequencies using time division multiplexing (TDM). Some of the signal pairs are delayed by one period within the TDM cycle to generate delayed signal pairs. The serial output is distributed, after the increase of the sample rate, to a plurality of filters to further increase the sample rate, each filter outputting a subset of the plurality of inputs using TDM. In one embodiment, the plurality of inputs includes 8 input pairs and the plurality of filters includes 6 Cascaded Integrator-Comb (CIC) filters operating in three-fold TDM. Further, one operation of the method combines the outputs from the plurality of filters with one of the signals from a corresponding signal pair or delayed signal pair. The result of the combination is sent to a digital to analog converter for transmission by one or more antennas.

    摘要翻译： 本发明的实施例提供了用于在集成电路（IC）中实现数字上变频器（DUC）的方法和系统。 该方法包括串行化多个输入以获得串行输出，然后增加串行输出的采样率。 另外，该方法使用时分多路复用（TDM）为期望的载频生成信号对（正弦，余弦）。 一些信号对在TDM周期内延迟一个周期以产生延迟的信号对。 串行输出在采样率增加之后被分配到多个滤波器以进一步增加采样率，每个滤波器使用TDM输出多个输入的子集。 在一个实施例中，多个输入包括8个输入对，并且多个滤波器包括以三重TDM操作的6个级联积分器（CIC）滤波器。 此外，该方法的一个操作将来自多个滤波器的输出与来自对应的信号对或延迟信号对的信号中的一个组合。 组合的结果被发送到数模转换器，用于由一个或多个天线传输。